TMS320C6713B Datasheet, PDF (22/153 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6713B
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS294B − OCTOBER 2005 − REVISED JUNE 2006
peripheral register descriptions (continued)
Table 12. McASP0 and McASP1 Registers
HEX ADDRESS RANGE
McASP0
McASP1
3C00 0000 − 3C00 FFFF 3C10 0000 − 3C10 FFFF
01B4 C000
01B4 C004
01B4 C008
01B4 C00C
01B4 C010
01B4 C014
01B4 C018
01B5 0000
01B5 0004
01B5 0008
01B5 000C
01B5 0010
01B5 0014
01B5 0018
01B4 C01C
01B5 001C
01B4 C020
01B4 C024 − 01B4 C040
01B4 C044
01B4 C048
01B4 C04C
01B4 C050
01B4 C054 − 01B4 C05C
01B4 C060
01B4 C064
01B4 C068
01B4 C06C
01B4 C070
01B4 C074
01B4 C078
01B4 C07C
01B4 C080
01B4 C084
01B4 C088
01B4 C08C − 01B4 C09C
01B4 C0A0
01B4 C0A4
01B4 C0A8
01B4 C0AC
01B4 C0B0
01B4 C0B4
01B5 0020
01B5 0024 − 01B5 0040
01B5 0044
01B5 0048
01B5 004C
01B5 0050
01B5 0054 − 01B5 005C
01B5 0060
01B5 0064
01B5 0068
01B5 006C
01B5 0070
01B5 0074
01B5 0078
01B5 007C
01B5 0080
01B5 0084
01B5 0088
01B5 008C − 01B5 009C
01B5 00A0
01B5 00A4
01B5 00A8
01B5 00AC
01B5 00B0
01B5 00B4
ACRONYM
REGISTER NAME
RBUF/XBUFx
McASPx receive buffer or McASPx transmit buffer via the
Peripheral Data Bus.
(Used when RSEL or XSEL bits = 0 [these bits are located
in the RFMT or XFMT registers, respectively].)
MCASPPIDx
Peripheral Identification register
[0x00100101 for McASP0 and for McASP1]
PWRDEMUx Power down and emulation management register
−
Reserved
−
Reserved
PFUNCx Pin function register
PDIRx
Pin direction register
PDOUTx Pin data out register
Pin data in / data set register
PDIN/PDSETx Read returns: PDIN
Writes affect: PDSET
PDCLRx Pin data clear register
−
Reserved
GBLCTLx Global control register
AMUTEx Mute control register
DLBCTLx Digital Loop-back control register
DITCTLx DIT mode control register
−
Reserved
RGBLCTLx
Alias of GBLCTL containing only Receiver Reset bits,
allows transmit to be reset independently from receive.
RMASKx Receiver format unit bit mask register
RFMTx
Receive bit stream format register
AFSRCTLx Receive frame sync control register
ACLKRCTLx Receive clock control register
AHCLKRCTLx High-frequency receive clock control register
RTDMx
Receive TDM slot 0−31 register
RINTCTLx Receiver interrupt control register
RSTATx
Status register − Receiver
RSLOTx Current receive TDM slot register
RCLKCHKx Receiver clock check control register
−
Reserved
XGBLCTLx
Alias of GBLCTL containing only Transmitter Reset bits,
allows transmit to be reset independently from receive.
XMASKx Transmit format unit bit mask register
XFMTx
Transmit bit stream format register
AFSXCTLx Transmit frame sync control register
ACLKXCTLx Transmit clock control register
AHCLKXCTLx High-frequency Transmit clock control register
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