TMS320C206 Datasheet, PDF (54/58 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
serial-port transmit timings (note: timings are for all SSP modes unless otherwise specified)
switching characteristics over recommended operating conditions [H = 0.5t_c(CO)] (see Figure 20)
PARAMETER
ALTERNATE
SYMBOL
’320C206-80
MIN TYP MAX
’320LC206-80
UNIT
MIN TYP MAX
Delay time, CLKX high
td(CLKX-DX) _{to DX valid}
tdis(DX-CLKX)
Disable time, DX valid
from CLKX high
th(CLKX-DX)
Hold time, DX valid
after CLKX high
tc(CLKX)
Cycle time, serial-port
clock (CLKX)
Internal CLKX
and internal
FSX
Internal CLKX
and external
FSX
External
CLKX and
internal FSX
External
CLKX and
external FSX
Multichannel
mode
SPI mode
td(DX)
td(DX)
tdis(DX)
th(DX)
Internal CLKX tc(SCK)
–5
22
–5
22
ns
0
20
0
20
–5
25
–5
4
10
–6
4H
–5
–5
–6
4H
25
4
10 ns
ns
ns
tf(CLKX)
Fall time, serial-port
clock (CLKX)
Internal CLKX tf(SCK)
5
5
ns
tr(CLKX)
Rise time, serial-port
clock (CLKX)
Internal CLKX tr(SCK)
tw(CLKX)
Pulse duration,
serial-port clock
(CLKX) low/high
Internal CLKX tw(SCK)
2H – 10
Internal CLKX
and internal
FSX
External
td(FS)
–5
td(CLKX-FX)
Delay time, CLKX rising _{CLKX and}
edge to FSX
internal FSX
Multichannel
mode†
5
SPI mode
–5
th(CLKXH-FX)
Hold time, FSX after
CLKX rising edge
Internal FSX th(FS)H
–5
† _{These timings also apply to the following pins in multichannel mode: CLKR, FSR, IO0.}
5
2H – 10
14
–5
18
5
4
–5
–5
5
ns
ns
14
ns
18
4
ns
54
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