TMS320C206 Datasheet, PDF (1/58 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
D High-Performance Static CMOS Technology
D Includes the ’320C2xLP Core CPU
D TMS320C206, TMS320LC206 are Members
of the ’C20x/’C2000 Platform Which Also
Includes the TMS320C203/LC203 and
TMS320F206 Devices
D Instruction-Cycle Time 25 ns at 3.3 V
D Source Code Compatible With TMS320C25
and other ’20x Devices
D Upwardly Code-Compatible With
TMS320C5x Devices
D Four External Interrupts
D TMS320C206, 5-V I/O (3.3-V core)
D TMS320LC206, 3.3-V core and I/O
D TMS320C206, TMS320LC206 Integrated
Memory:
– 544 × 16 Words of On-Chip Dual-Access
Data RAM
– 32K × 16 Words of On-Chip ROM
– 4K × 16 Words of On-Chip Single-Access
Program/ Data RAM
D 224K × 16-Bit Maximum Addressable
External Memory Space
– 64K Program
– 64K Data
– 64K Input/Output (I/O)
– 32K Global
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
D 32-Bit Arithmetic Logic Unit (ALU )
Accumulator
D 16 × 16-Bit Multiplier With a 32-Bit Product
D Block Moves from Data and Program
Space
D TMS320C206, TMS320LC206 Peripherals:
– On-Chip 20-Bit Timer
– On-Chip Software-Programmable
Wait-State (0 to 7) Generator
– On-Chip Oscillator
– On-Chip Phase-Locked Loop (PLL)
– Six General-Purpose I/O Pins
– Full-Duplex Asynchronous Serial Port
(UART)
– Enhanced Synchronous Serial Port
(ESSP) With Four-Level-Deep FIFOs
D Input Clock Options
   – Options: Multiply-by-One, -Two, or -Four,
and Divide-by-Two ( 1, 2, 4, and 2)
D Support of Hardware Wait States
D Power Down IDLE Mode
D IEEE 1149.1^†-Compatible Scan-Based
Emulation
D TMS320C206, TMS320LC206 100-Pin PZ
Package, Small Thin Quad Flat Package
(TQFP)
D Industrial Temperature Version Planned,
(– 40°C to 85°C)
description
The Texas Instruments (TI™) TMS320C206^‡ and TMS320LC206^‡ digital signal processors (DSPs) are
fabricated with static CMOS integrated-circuit technology. The architectural design is based upon that of the
TMS320C20x series and is optimized for low-power operation. The combination of advanced Harvard
architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the
operational flexibility and speed of the ’C206.
The ’C206 offers these advantages:
D Enhanced TMS320 architectural design for increased performance and versatility
D Advanced integrated-circuit processing technology for increased performance
D ’C206 devices are pin- and code-compatible with ’C203 and ’F206 devices.
D Source code for the ’C206 DSPs is software-compatible with the ’C1x and ’C2x DSPs and is upwardly
compatible with fifth-generation DSPs (’C5x)
D New static-design techniques for minimizing power consumption and increasing radiation tolerance
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† _{IEEE Standard 1149.1 - 1990, IEEE Standard Test-Access Port}
‡ _{Device numbers are hereafter referred to in the data sheet as ’C206, unless otherwise specified.}
TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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