TMS320C206 Datasheet, PDF (44/58 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
timing at V_DD = 3.3 V/5 V with the PLL circuit enabled (’C206/’LC206)
PARAMETER
Input clock frequency, multiply-by-one
fx
Input clock frequency, multiply-by-two
Input clock frequency, multiply-by-four
TEST CONDITIONS
TA = –40°C to 85°C, 3.3 V/5 V
MIN MAX
4 40.96
4 20.48
4 10.24
UNIT
MHz
switching characteristics over recommended operating conditions [H = 0.5t_c(CO)] (see Figure 11)
PARAMETER
tc(CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
td(TP)
Cycle time, CLKOUT1
Fall time, CLKOUT1
Rise time, CLKOUT1
Pulse duration, CLKOUT1 low
Pulse duration, CLKOUT1 high
Delay time, transitory phase—PLL synchronized after CLKIN
supplied
MIN
25
H–3
H–3
’320C206-80
’320LC206-80
TYP
5
5
H
H
MAX
†
H+3
H+3
UNIT
ns
ns
ns
ns
ns
5000 cycles
† _{Static design tc(CI) can approach ∞}
timing requirements (see Figure 11)
tc(CI)
tf(CI)
tr(CI)
tw(CIL)
tw(CIH)
Cycle time, CLKIN multiply-by-one
Cycle time, CLKIN multiply-by-two
Cycle time, CLKIN multiply-by-four
Fall time, CLKIN
Rise time, CLKIN
Pulse duration, CLKIN low
Pulse duration, CLKIN high
tw(CIH)
’320C206-80
’320LC206-80
MIN
MAX
25
50
100
4
4
12
125
12
125
UNIT
ns
ns
ns
ns
ns
ns
ns
tc(CI)
tw(CIL)
CLKIN
CLKOUT1
tc(CO)
tw(COH)
tf(CI)
tw(COL)
tf(CO)
tr(CO)
Figure 11. CLKIN-to-CLKOUT1 Timing With PLL ( Enabled )
tr(CI)
44
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