PCI4520 Datasheet, PDF (54/211 Pages) Texas Instruments – DUAL-SOCKET PC CARD AND INTEGRATED 1394A-2000 OHCI TWO-PORT PHY/LINK-LAYER CONTROLLER

between the three PCI4520 functions, and only one write to function 0 or 1 is necessary to configure the
MFUNC6–MFUNC0 signals. Writing to functions 0 and 1 only is recommended. See Section 4.34, Multifunction
Routing Status Register, for details on configuring the multifunction terminals.
The parallel ISA-type IRQ signaling from the MFUNC6–MFUNC0 terminals is compatible with the input signal
requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs.
Design constraints may demand more MFUNC6–MFUNC0 IRQ terminals than the PCI4520 device makes available.
3.7.4 Using Parallel PCI Interrupts
Parallel PCI interrupts are available when in pure PCI interrupt mode and are routed on MFUNC terminals
(MFUNC0–MFUNC2). The PCI interrupt signaling is independent upon the interrupt mode and is summarized in
Table 3–9. The interrupt mode is selected in the device control register (PCI offset 92h, see Section 4.37).
Table 3–9. Interrupt Pin Register Cross Reference
INTERRUPT SIGNALING MODE
Parallel PCI interrupts only
Reserved
IRQ serialized (IRQSER) and parallel PCI interrupts
IRQ and PCI serialized (IRQSER) interrupts (default)
INTPIN
FUNCTION 0
FUNCTION 1
01h (INTA)
02h (INTB)
01h (INTA)
02h (INTB)
01h (INTA)
01h (INTA)
01h (INTA)
02h (INTB)
3.7.5 Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the PCI4520 device uses a single terminal to communicate all
interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle,
multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The
packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For
details on the IRQSER protocol, refer to the document Serialized IRQ Support for PCI Systems.
3.7.6 SMI Support in the PCI4520 Device
The PCI4520 device provides a mechanism for interrupting the system when power changes have been made to the
PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI)
scheme. SMI interrupts are generated by the PCI4520 device, when enabled, after a write cycle to either the socket
control register (CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA power control register (ExCA
offset 02h/42h/802h, see Section 5.3) causes a power cycle change sequence to be sent on the power switch
interface.
The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.28).
These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3–10 describes the SMI control
bits function.
BIT NAME
SMIROUTE
SMISTAT
SMIENB
Table 3–10. SMI Control
FUNCTION
This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.
This socket dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1.
When set, SMI interrupt generation is enabled. This bit is shared by functions 0 and 1.
If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt
can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register (ExCA offset
1Eh/5Eh/81Eh, see Section 5.20).
If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data
slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either
MFUNC3 or MFUNC6 through the multifunction routing status register (PCI offset 8Ch, see Section 4.34).
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