PCI4520 Datasheet, PDF (36/211 Pages) Texas Instruments – DUAL-SOCKET PC CARD AND INTEGRATED 1394A-2000 OHCI TWO-PORT PHY/LINK-LAYER CONTROLLER

Table 2–14. CardBus PC Card Interface Control Terminals
SOCKET A
TERMINAL
NAME
NO.
A_CAUDIO F03
SOCKET B
TERMINAL
NAME
NO.
B_CAUDIO C15
I/O
DESCRIPTION
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker.
I The PCI4520 device supports the binary audio mode and outputs a binary signal from
the card to SPKROUT.
A_CBLOCK A07 B_CBLOCK H18 I/O CardBus lock. CBLOCK is used to gain exclusive access to a target.
A_CCD1
A_CCD2
B13
F01
B_CCD1
B_CCD2
P17
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with
B15 ^{I CVS1 and CVS2 to identify card insertion and interrogate cards to determine the}
operating voltage and card type.
CardBus device select. The PCI4520 device asserts CDEVSEL to claim a CardBus
A_CDEVSEL
B06
B_CDEVSEL
G19
I/O
cycle as the target device. As a CardBus initiator on the bus, the PCI4520 device
monitors CDEVSEL until a target responds. If no target responds before timeout occurs,
then the PCI4520 device terminates the cycle with an initiator abort.
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle.
A_CFRAME
F06
B_CFRAME
F19
I/O ^{CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers}
continue while this signal is asserted. When CFRAME is deasserted, the CardBus bus
transaction is in the final data phase.
A_CGNT
F07
B_CGNT
H15
O
CardBus bus grant. CGNT is driven by the PCI4520 device to grant a CardBus PC Card
access to the CardBus bus after the current data transaction has been completed.
A_CINT
G06
B_CINT
B16
I
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt
servicing from the host.
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete
A_CIRDY
A05
B_CIRDY
G14
I/O
the current data phase of the transaction. A data phase is completed on a rising edge
of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both
sampled asserted, wait states are inserted.
CardBus parity error. CPERR reports parity errors during CardBus transactions, except
A_CPERR B07 B_CPERR H17 I/O during special cycles. It is driven low by a target two clocks following the data cycle during
which a parity error is detected.
A_CREQ
B02
B_CREQ
D17
I ^{CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use}
of the CardBus bus as an initiator.
CardBus system error. CSERR reports address parity errors and other system errors
that could lead to catastrophic results. CSERR is driven by the card synchronous to
A_CSERR E02 B_CSERR A16 I CCLK, but deasserted by a weak pullup; deassertion may take several CCLK periods.
The PCI4520 device can report CSERR to the system by assertion of SERR on the PCI
interface.
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the
A_CSTOP C07 B_CSTOP H14 I/O current CardBus transaction. CSTOP is used for target disconnects, and is commonly
asserted by target devices that do not support burst data transfers.
A_CSTSCHG F02 B_CSTSCHG E14
I
CardBus status change. CSTSCHG alerts the system to a change in the card status, and
is used as a wake-up mechanism.
CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the
A_CTRDY
C06
B_CTRDY
G17 I/O ^{current data phase of the transaction. A data phase is completed on a rising edge of}
CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are
inserted.
A_CVS1
A_CVS2
F05
A03
B_CVS1
B_CVS2
B17
E18
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in
I/O conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to
determine the operating voltage and card type.
2–19