PCI4520 Datasheet, PDF (111/211 Pages) Texas Instruments – DUAL-SOCKET PC CARD AND INTEGRATED 1394A-2000 OHCI TWO-PORT PHY/LINK-LAYER CONTROLLER

5.8 ExCA I/O Window Control Register
The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See
Table 5–10 for a complete description of the register contents.
Bit
Name
Type
Default
BIT
7
6
5
4
3
2
1
0
7
RW
0
Register:
Offset:
Type:
Default:
SIGNAL
WAITSTATE1
ZEROWS1
IOIS16W1
DATASIZE1
WAITSTATE0
ZEROWS0
IOIS16W0
DATASIZE0
6
5
4
3
2
1
0
ExCA I/O window control
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
ExCA I/O window control
CardBus socket address + 807h; Card A ExCA offset 07h
Card B ExCA offset 47h
Read/Write
00h
Table 5–10. ExCA I/O Window Control Register Description
TYPE
RW
RW
FUNCTION
I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This
bit is encoded as:
0 = 16-bit cycles have standard length (default).
1 = 16-bit cycles are extended by one equivalent ISA wait state.
I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
0 = 8-bit cycles have standard length (default).
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data sizing feature that uses the
IOIS16 signal from the PC Card to determine the data width of the I/O data transfer. This bit is encoded
RW as:
0 = Window data width is determined by bit 4 (DATASIZE1) (default).
1 = Window data width is determined by the IOIS16 signal.
I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if bit 5 (IOIS16W1) is set.
RW ^{This bit is encoded as:}
0 = Window data width is 8 bits (default).
1 = Window data width is 16 bits.
I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This
RW bit is encoded as:
0 = 16-bit cycles have standard length (default).
1 = 16-bit cycles are extended by one equivalent ISA wait state.
I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
RW 82365SL-DF. This bit is encoded as:
0 = 8-bit cycles have standard length (default).
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses the
IOIS16 signal from the PC Card to determine the data width of the I/O data transfer. This bit is encoded
RW as:
0 = Window data width is determined by bit 0 (DATASIZE0) (default).
1 = Window data width is determined by the IOIS16 signal.
I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if bit 1 (IOIS16W0) is set.
RW ^{This bit is encoded as:}
0 = Window data width is 8 bits (default).
1 = Window data width is 16 bits.
5–12