TMS320C6747CZKBD4 Datasheet, PDF (52/227 Pages) Texas Instruments – TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor

TMS320C6745, TMS320C6747
SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013
www.ti.com
Table 2-25. General Purpose Input Output Terminal Functions (continued)
SIGNAL NAME
USB0_DRVVBUS/GP4[15]
AMUTE1/EPWMTZ/GP4[14]
AFSR1/GP4[13]
ACLKR1/ECAP2/APWM2/GP4[12]
AHCLKR1/GP4[11]
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
AXR1[9]/GP4[9]
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
AXR1[4]/EQEP1B/GP4[4]
AXR1[3]/EQEP1A/GP4[3]
AXR1[2]/GP4[2]
AXR1[1]/GP4[1]
AXR1[0]/GP4[0]
EMB_WE_DQM[0]/GP5[15]
EMB_WE_DQM[1]/GP5[14]
SPI1_SCS[0]/UART2_TXD/GP5[13]
SPI1_ENA/UART2_RXD/GP5[12]
AXR1[11]/GP5[11]
AXR1[10]/GP5[10]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
PIN NO
PTP ZKB
GP4
-
E4
132 D4
166 L3
165 L2
-
L1
163 K4
-
M1
168 M2
169 M3
170 M4
171 N1
173 N2
174 P1
175 P2
176 R2
1
T3
GP5
60 K14
85 C15
8
P4
7
R4
6
T4
4
N3
2
R3
3
P3
16
T6
14 N5
13 P5
9
N4
12 R5
11
T5
18 P6
17 R6
TYPE⁽¹⁾ PULL⁽²⁾
MUXED
DESCRIPTION
O
IPD USB0
McASP1,
O
IPD
eHRPWM0,
eHRPWM1,
eHRPWM2
I/O
IPD McASP1
I/O
IPD McASP1, eCAP2
I/O
IPD McASP1
I/O
IPD
McASP1,
eHRPWM0
I/O
IPD McASP1
I/O
IPD
McASP1,
eHRPWM1 A
GPIO Bank 4
I/O
IPD
McASP1,
eHRPWM1 B
I/O
IPD
McASP1,
eHRPWM2 A
I/O
IPD
McASP1,
eHRPWM2 B
I/O
IPD
McASP1, eQEP
I/O
IPD
I/O
IPD
I/O
IPD McASP1
I/O
IPD
O
IPU
EMIFB
O
IPU
O
IPU
SPI1, UART2
I
IPU
I/O
IPU
McASP1
I/O
IPU
I
IPU _{UART0, I2C0,}
O
IPU ^BOOT
I
IPD
SPI1, eQEP1,
BOOT
GPIOBank 5
I/O
IPU _{SPI1, I2C1,}
I/O
IPU ^BOOT
I
IPU _{SPI0, UART0,}
I
IPU ^{eQEP0, BOOT}
I
IPD
SPI0, eQEP1,
BOOT
I
IPD _{SPI0, eQEP0,}
I
IPD ^BOOT
52
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