TMS320C6747CZKBD4 Datasheet, PDF (142/227 Pages) Texas Instruments – TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor

TMS320C6745, TMS320C6747
SPRS377E – SEPTEMBER 2008 – REVISED FEBRUARY 2013
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Table 5-63. General Timing Requirements for SPI1 Slave Modes⁽¹⁾ (continued)
No.
12 t_{su(SOMI_SPC)S}
13 t_{d(SPC_SOMI)S}
14 t_{oh(SPC_SOMI)S}
15 t_{su(SIMO_SPC)S}
16 t_{ih(SPC_SIMO)S}
PARAMATER
Setup time, transmit data written to
SPI before initial clock edge from
master.^{(2) (3)}
Delay, subsequent bits valid on
SPI1_SOMI after transmit edge of
SPI1_CLK
Output hold time, SPI1_SOMI valid
after
receive edge of SPI1_CLK
Input Setup Time, SPI1_SIMO valid
before
receive edge of SPI1_CLK
Input Hold Time, SPI1_SIMO valid
after
receive edge of SPI1_CLK
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK rising
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK falling
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
Polarity = 0, Phase = 0,
to SPI1_CLK falling
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
MIN
MAX UNIT
2P
2P
ns
2P
2P
19
19
ns
19
19
0.5t_c(SPC)S -3
0.5t_c(SPC)S -3
ns
0.5t_c(SPC)S -3
0.5t_c(SPC)S -3
0
0
ns
0
0
5
5
ns
5
5
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.
142 Peripheral Information and Electrical Specifications
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