AFE7222_15 Datasheet, PDF (52/106 Pages) Texas Instruments – Analog Front End Wideband Mixed-Signal Transceiver

AFE7222
AFE7225
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
DFS_RX
0
1
DATA FORMAT
2s-complememt
straight offset binary
MSB_FIRST_RX: Flips the out data order to MSB first.
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MSB_FIRST_RX
0
1
DATA ORDER
LSB first
MSB first
TWOWIRE_RX: Configure the device to give data in two wire mode.
SDR_RX: Configure the device to give data in SDR mode.
Register Name – CONFIG132 – Address 0x33B, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
HALFX_IN_2WIRE_RX
<0>
BITWISE_RX
All the modes of register 0x33B work only if MASTER_OVERRIDE_RX (Bit <7> in Address 0x33A) is
enabled.
BITWISE_RX: Configure the device to give data in bit wise mode.
HALFX_IN_2WIRE_RX: Makes the frame clock output 0.5X (default is 1X). To be used when in wordwise
mode.
Register Name – CONFIG133 – Address 0x23A, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
CLK_STR_2X DATA_STR_2X
CLK_STR_RX: When set, the LVDS clock buffers has double strength (to be used with 50 ohms external
termination)
DATA_STR_2X: When set, all the LVDS clock buffers have double strength (to be used with 50 ohms
external termination)
Register Name – CONFIG134 – Address 0x001, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
LVDS_SWING<5:0>
5.9 AUX ADC REGISTERS
Register Name – CONFIG135 – Address 0x364, Default = 0x00
<7>
<6>
<5>
<4>
SHIGH_WIDTH<1:0>
NO_OF_SAMPLES_AVGED<1:0>
<3>
<2>
<1>
NO_OF_SAMPLES<2:0>
SHIGH_WIDTH<1:0>: No. of clock cycles width of sampling clock.
<0>
CONV_START
SHIGH_WIDTH<1:0>
00
01
10
11
NO.OF CLOCK CYCLE WIDTH
15(default)
30
60
150
NO_OF_SAMPLES<2:0>: No. of samples to convert in 1 conversion cycle.
52
REGISTER DESCRIPTIONS
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