AFE7222_15 Datasheet, PDF (17/106 Pages) Texas Instruments – Analog Front End Wideband Mixed-Signal Transceiver

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AFE7222
AFE7225
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
Table 3-1. LVDS Timings at Lower Sampling Frequencies
Sampling Frequency, MSPS
20
35
50
65
80
95
110
125
Fs ≤ 125MSPS
Sampling Frequency, MSPS
10
20
30
40
50
65
Fs ≤ 65MSPS
Sampling Frequency, MSPS
20
35
50
65
2-WIRE MODE DDR CLOCK
Setup time, ns
MIN
TYP
MAX
3.75
3.93
1.99
2.18
1.28
1.46
0.84
1.06
0.59
0.81
0.46
0.67
0.31
0.52
0.29
0.42
Clock propagation delay, t_PDI = t_DELAY
11.5
13.8
15.5
2-WIRE MODE, SDR CLOCK
Setup time, ns
MIN
TYP
MAX
8.14
8.32
3.89
4.08
2.33
2.6
1.68
1.91
1.22
1.48
0.85
1.08
Clock propagation delay, t_PDI = 0.5*Ts + t_DELAY
1-WIRE MODE, DDR CLOCK
Setup time, ns
MIN
TYP
MAX
1.71
1.90
0.77
0.99
0.36
0.61
0.25
0.39
Fs ≤ 65MSPS
Clock propagation delay, t_PDI = 0.5*Ts + t_DELAY
MIN
3.64
1.96
1.28
0.85
0.70
0.49
0.36
0.30
11.5
MIN
7.90
3.85
2.51
1.81
1.41
1.08
11.5
MIN
1.67
0.82
0.39
0.26
MIN
11.50
Hold time, ns
TYP
3.9
2.2
1.51
1.14
0.90
0.70
0.58
0.47
t_DELAY, ns
13.8
Hold time, ns
TYP
8.06
4.01
2.71
2.03
1.64
1.21
t_DELAY, ns
14
Hold time, ns
TYP
1.92
1.04
0.62
0.40
t_DELAY, ns
TYP
13.50
MAX
15.5
MAX
16.5
MAX
MAX
15.50
Table 3-2. CMOS Timings at Lower Sampling Frequencies
Sampling Frequency, MSPS
20
40
65
90
105
Fs ≤ 105MSPS
Timings specified with respect to CLKOUT
Setup time, ns
Hold time, ns
MIN
TYP
MAX
MIN
TYP
10.90
11.50
11.22
11.60
4.62
5.25
4.99
5.33
2.06
2.66
2.46
2.86
1
1.9
1.8
2.3
0.5
1.4
1.4
1.8
t_DELAY, ns
Clock propagation delay, t_PDI = 0.5*Ts + t_DELAY
MIN
TYP
14
16.50
MAX
MAX
19
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