ADS6145 Datasheet, PDF (52/68 Pages) Texas Instruments – 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS6145, ADS6144
ADS6143, ADS6142
SLWS198A – JULY 2007 – REVISED OCTOBER 2007
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DDR LVDS Interface
The LVDS interface works only with a 3.3-V DRVDD supply. In this mode, the 14 data bits and the output clock
are available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits are multiplexed and
output on each LVDS differential pair every clock cycle (DDR - Double Data Rate, see Figure 105 ). So, there
are 7 LVDS output pairs for the 14 data bits and 1 LVDS output pair for the output clock.
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV
single-ended voltage swing (700-mV_PP differential swing). The LVDS buffer currents can also be programmed to
2.5 mA, 4.5 mA, and 1.75 mA (register bits <LVDS CURRENT>, see Table 11). In addition, there is a current
double mode, where this current is doubled for the data and output clock buffers (register bits <CURRENT
DOUBLE>, see Table 11).
Pins
CLKOUTP
CLKOUTM
Output Clock
14-Bit ADC Data
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
D12_D13_P
D12_D13_M
Data bits D0, D1
Data bits D2, D3
Data bits D4, D5
Data bits D6, D7
Data bits D8, D9
Data bits D10, D11
Data bits D12, D13
ADS614x
Figure 105. DDR LVDS Outputs
52
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