ADS6145 Datasheet, PDF (32/68 Pages) Texas Instruments – 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS6145, ADS6144
ADS6143, ADS6142
SLWS198A – JULY 2007 – REVISED OCTOBER 2007
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TYPICAL CHARACTERISTICS - ADS6143 (F_S= 80 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V_PP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
100
96
92
88
Gain = 3.5 dB
84
80
76
Gain = 0 dB
72
68
64
60
0 50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G043
Figure 51.
SFDR vs INPUT FREQUENCY ACROSS GAINS
95
Input adjusted to get −1dBFS input
90
3 dB
85
2 dB 6 dB
80
0 dB
75
1 dB
70
5 dB
4 dB
65
60
0
100
200
300
400
f_IN − Input Frequency − MHz
Figure 53.
500
G045
PERFORMANCE vs AVDD
88
f_IN = 70.1 MHz
86 _{DRVDD = 3.3 V}
SFDR
84
82
SNR
80
78
76
74
72
3.0
3.1
3.2
3.3
3.4
3.5
AV_DD − Supply Voltage − V
Figure 55.
78
77
76
75
74
73
72
71
70
3.6
G047
SNR vs INPUT FREQUENCY (LVDS interface)
76
74
Gain = 0 dB
72
70
Gain = 3.5 dB
68
66
64
62
0
50 100 150 200 250 300 350 400 450 500
f_IN − Input Frequency − MHz
G044
Figure 52.
SINAD vs INPUT FREQUENCY ACROSS GAINS
76
0 dB Input adjusted to get −1dBFS input
74
1 dB
72
2 dB
70
3 dB
68
66
64
4 dB _{5 dB}
6 dB
62
60
0
100
200
300
400
f_IN − Input Frequency − MHz
Figure 54.
500
G046
PERFORMANCE vs DRVDD
102
77
f_IN = 10.1 MHz
100 AV_DD = 3.3 V
76
SNR
98
75
96
74
94
73
SFDR
92
72
90
71
88
70
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
DRV_DD − Supply Voltage − V
G048
Figure 56.
32
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