ADS6145 Datasheet, PDF (11/68 Pages) Texas Instruments – 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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Input
Signal
Input
Clock
CLKP
CLKM
N+3
N+4
N+2
Sample
N+1
N
t_a
ADS6145, ADS6144
ADS6143, ADS6142
SLWS198A – JULY 2007 – REVISED OCTOBER 2007
N+10
N+11
N+12
N+9
CLKOUTM
CLKOUTP
DDR
LVDS
Output Data
DXP, DXM
9 Clock Cycles
EOEOEOEOEOE
t_su
t_h
t_PDI
OEOEOEOEO
E – Even Bits D0,D2,D4,D6,D8,D10,D12
N–9
N–8
N–7
N–6
N–5
O – Odd Bits D1,D3,D5,D7,D9,D11,D13
CLKOUT
Parallel
CMOS
Output Data
D0–D13
9 Clock Cycles
N–9
N–8
N–7
N–6
N–5
N–1
N
N+1
N+2
t_PDI
t_su
t_h
N–1
N
N+1
N+2
Figure 1. Latency
Input
Clock
Output
Clock
Output
Data Pair
CLKM
CLKP
CLKOUTM
CLKOUTP
t_su
Dn_Dn+1_P,
Dn_Dn+1_M
t_PDI
t_h
Dn⁽¹⁾
t_su
t_h
Dn+1⁽²⁾
(1)_{Dn – Bits D0, D2, D4, D6, D8, D10, D12}
(2)_{Dn+1 – Bits D1, D3, D5, D7, D9, D11, D13}
Figure 2. LVDS Mode Timing
Input
Clock
CLKM
CLKP
Output
Clock
CLKOUT
Output
Data
Dn
t_PDI
t_h
t_su
Dn⁽¹⁾
(1)_{Dn – Bits D0–D13}
Figure 3. CMOS Mode Timing
Copyright © 2007, Texas Instruments Incorporated
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