TMS320C6727B_0807 Datasheet, PDF (50/118 Pages) Texas Instruments – Floating-Point Digital Signal Processors

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008
Table 4-7. 133-MHz EMIF SDRAM Interface Timing Requirements⁽¹⁾
NO.
MIN
19 t_{su(EM_DV-EM_CLKH)}
20 t_{h(EM_CLKH-EM_DIV)}
Input setup time, read data valid on D[31:0] before EM_CLK rising
0.4
Input hold time, read data valid on D[31:0] after EM_CLK rising
1.9
(1) For more information about supported EMIF frequency, see Table 2-1.
Table 4-8. 133-MHz EMIF SDRAM Interface Switching Characteristics⁽¹⁾
NO.
PARAMETER
1
t_{c(EM_CLK)}
2
t_{w(EM_CLK)}
3
t_{d(EM_CLKH-EM_CSV)S}
4
t_{oh(EM_CLKH-EM_CSIV)S}
5
t_{d(EM_CLKH-EM_WE-DQMV)S}
6
t_{oh(EM_CLKH-EM_WE-DQMIV)S}
7
t_{d(EM_CLKH-EM_AV)S}
8
t_{oh(EM_CLKH-EM_AIV)S}
Cycle time, EMIF clock EM_CLK
Pulse width, EMIF clock EM_CLK high or low
Delay time, EM_CLK rising to EM_CS[0] valid
Output hold time, EM_CLK rising to EM_CS[0] invalid
Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid
Output hold time, EM_CLK rising to EM_WE_DQM[3:0] invalid
Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid
Output hold time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0]
invalid
9
t_{d(EM_CLKH-EM_DV)S}
10 t_{oh(EM_CLKH-EM_DIV)S}
11 t_{d(EM_CLKH-EM_RASV)S}
12 t_{oh(EM_CLKH-EM_RASIV)S}
13 t_{d(EM_CLKH-EM_CASV)S}
14 t_{oh(EM_CLKH-EM_CASIV)S}
15 t_{d(EM_CLKH-EM_WEV)S}
16 t_{oh(EM_CLKH-EM_WEIV)S}
17 t_{dis(EM_CLKH-EM_DHZ)S}
18 t_{ena(EM_CLKH-EM_DLZ)S}
Delay time, EM_CLK rising to EM_D[31:0] valid
Output hold time, EM_CLK rising to EM_D[31:0] invalid
Delay time, EM_CLK rising to EM_RAS valid
Output hold time, EM_CLK rising to EM_RAS invalid
Delay time, EM_CLK rising to EM_CAS valid
Output hold time, EM_CLK rising to EM_CAS invalid
Delay time, EM_CLK rising to EM_WE valid
Output hold time, EM_CLK rising to EM_WE invalid
Delay time, EM_CLK rising to EM_D[31:0] 3-stated
Output hold time, EM_CLK rising to EM_D[31:0] driving
(1) For more information about supported EMIF frequency, see Table 2-1.
MIN
7.5
2.25
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
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MAX UNIT
ns
ns
MAX UNIT
ns
ns
5.1 ns
ns
5.1 ns
ns
5.1 ns
ns
5.1 ns
ns
5.1 ns
ns
5.1 ns
ns
5.1 ns
ns
5.1 ns
ns
50
Peripheral and Electrical Specifications
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