TMS320C6727B_0807 Datasheet, PDF (32/118 Pages) Texas Instruments – Floating-Point Digital Signal Processors

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008
www.ti.com
Table 3-5. Priority of Control of Data Output on Multiplexed Pins
PIN
SPI0_SOMI/I2C0_SDA
SPI0_CLK/I2C0_SCL
SPI0_SCS/I2C1_SCL
SPI0_ENA/I2C1_SDA
AXR0[5]/SPI1_SCS
AXR0[6]/SPI1_ENA
AXR0[7]/SPI1_CLK
AXR0[8]/AXR1[5]/SPI1_SOMI
AXR0[9]/AXR1[4]/SPI1_SIMO
AXR0[10]/AXR1[3]
AXR0[11]/AXR1[2]
AXR0[12]/AXR1[1]
AXR0[13]/AXR1[0]
AXR0[14]/AXR2[1]
AXR0[15]/AXR2[0]
AHCLKR0/AHCLKR1
AHCLKX0/AHCLKX2
AMUTE2/HINT
HD[16]/HHWIL
EM_D[31:16]/UHPI_HA[15:0] ⁽¹⁾
FIRST PRIORITY
SPI0_SOMI
SPI0_CLK
SPI0_SCS
SPI0_ENA
AXR0[5]
AXR0[6]
AXR0[7]
AXR0[8]
AXR0[9]
AXR0[10]
AXR0[11]
AXR0[12]
AXR0[13]
AXR0[14]
AXR0[15]
AHCLKR0
AHCLKX0
AMUTE2
HD[16]
EM_D[31:16] (Disabled if
CFGHPI.NMUX=1)
SECOND PRIORITY
I2C0_SDA
I2C0_SCL
I2C1_SCL
I2C1_SDA
SPI1_SCS
SPI1_ENA
SPI1_CLK
AXR1[5]
AXR1[4]
AXR1[3]
AXR1[2]
AXR1[1]
AXR1[0]
AXR2[1]
AXR2[0]
AHCLKR1
AHCLKX2
HINT
HHWIL
UHPI_HA[15:0] (Input Only)
THIRD PRIORITY
SPI1_SOMI
SPI1_SIMO
(1) When using the UHPI in non-multiplexed mode, ensure EM_D[31:16] are configured as inputs so that these pins may be used as
UHPI_HA[15:0]. To ensure this, you must set the CFGHPI.NMUX bit to a '1' before the EMIF SDRAM initialization completes;
otherwise, a drive conflict will occur. [The EMIF bus parking function drives the data bus in between accesses.]
32
Device Configurations
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