TMS320C6727B_0807 Datasheet, PDF (18/118 Pages) Texas Instruments – Floating-Point Digital Signal Processors

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008
www.ti.com
Figure 2-7 shows the bit layout of the CFGPIN1 register and Table 2-11 contains a description of the bits.
31
8
Reserved
7
PINCAP15
6
PINCAP14
5
PINCAP13
4
PINCAP12
3
PINCAP11
2
PINCAP10
1
PINCAP9
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 2-7. CFGPIN1 Register Bit Layout (0x4000 0004)
0
PINCAP8
Table 2-11. CFGPIN1 Register Bit Field Description (0x4000 0004)
BIT NO.
31:8
7
6
5
4
3
2
1
0
NAME
Reserved
PINCAP15
PINCAP14
PINCAP13
PINCAP12
PINCAP11
PINCAP10
PINCAP9
PINCAP8
DESCRIPTION
Reads are indeterminate. Only 0s should be written to these bits.
AXR0[5]/SPI1_SCS pin state captured on rising edge of RESET pin.
AXR0[6]/SPI1_ENA pin state captured on rising edge of RESET pin.
UHPI_HCS pin state captured on rising edge of RESET pin.
UHPI_HD[0] pin state captured on rising edge of RESET pin.
EM_D[16]/UHPI_HA[0] pin state captured on rising edge of RESET pin.
AFSX0 pin state captured on rising edge of RESET pin.
AFSR0 pin state captured on rising edge of RESET pin.
AXR0[0] pin state captured on rising edge of RESET pin.
18
Device Overview
Submit Documentation Feedback