ADS62P15_1 Datasheet, PDF (50/63 Pages) Texas Instruments – Dual Channel 11-Bits,125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs

ADS62P15
SLAS572B – OCTOBER 2007 – REVISED APRIL 2009 .................................................................................................................................................... www.ti.com
Decimation Filters
ADS62P15 includes option to decimate the ADC output data with in-built low pass, high pass or band pass filters.
The decimation rate and type of filter can be selected using register bits (DECIMATION RATE) and
(DECIMATION FILTER TYPE). Decimation rates of 2, 4 or 8 are available and either low pass, high pass or
band pass filters can be selected (see Table 12). By default, the decimation filter is disabled – use register bit
<DECIMATION ENABLE> to enable it.
Table 12. Decimation Filter Modes
COMBINATION OF DECIMATION RATES AND FILTER TYPES
DECIMATION
TYPE OF FILTER
Decimate by 2
Decimate by 4
In-built low pass filter (pass band = 0 to Fs/4)
In-built high pass filter (pass band = Fs/4 to Fs/2)
In-built low pass filter (pass band = 0 to Fs/8)
In-built 2^nd band pass filter (pass band = Fs/8 to Fs/4)
In-built 3^rd band pass filter (pass band = Fs/4 to 3Fs/8)
In-built last band pass filter (pass band = 3Fs/8 to Fs/2)
<DECIMATION
RATE>
000
000
001
001
001
001
<DECIMATIO
N FILTER
FREQ
BAND>
<FILTER
COEFF
SELECT
>
<DECIMATI
ON
ENABLE>
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
Decimate by 2
Decimate by 4
Decimate by 8
No decimation
Custom filter (user programmable coefficients)
Custom filter (user programmable coefficients)
Custom filter (user programmable coefficients)
Custom filter (user programmable coefficients)
000
X
X
1
1
001
X
X
1
1
100
X
X
1
1
011
X
X
1
0
Decimation Filter Equation
The decimation filter is implemented as 24-tap FIR with symmetrical coefficients (each coefficient is 12-bit
signed). The filter equation is:
y(n) +
ǒ Ǔ1
2¹¹
[h0 x(n) ) h1 x(n * 1) ) h2 x(n * 2) ) AAA ) h11 x(n * 11) ) h11 x(n * 12) ) AAA ) h1 x(n * 22) ) h0 x(n * 23)]
(3)
By setting the register bit <ODD TAP ENABLE> = 1, a 23-tap FIR is implemented:
y(n) +
ǒ Ǔ1
2¹¹
x[h0
x(n) ) h1
x(n * 1) ) h2
x(n * 2) ) AAA ) h10
x(n * 10) ) h11
x(n * 11) ) h10
x(n * 12) ) AAA ) h1
x(n * 21) ) h0
x(n * 22)]
(4)
In the above equations,
h0, h1 …h11 are 12-bit signed representation of the coefficients,
x(n) is the input data sequence to the filter
y(n) is the filter output sequence
Pre-defined Coefficients
The in-built filter types (low pass, high pass and band pass) use pre-defined coefficients. The frequency
response of the in-built filters is shown in Figure 51 and Figure 52.
50
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