ADS62P15_1 Datasheet, PDF (25/63 Pages) Texas Instruments – Dual Channel 11-Bits,125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs

ADS62P15
www.ti.com .................................................................................................................................................... SLAS572B – OCTOBER 2007 – REVISED APRIL 2009
A7–A0
(hex)
1A
D2–D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
D6-D4
000
001
010
011
100
101
110
111
D7
0
1
Table 11.
D7
D6
D5
D4
D3
D2
D1
D0
<LOW LATENCY>
<OFFSET TC>
Offset correction time constant
<GAIN CORRECTION>
0 to 0.5 dB, steps of 0.05 dB
<GAIN CORRECTION> Enables fine gain correction in steps of 0.05 dB (same correction applies to both channels)
0 dB gain, default after reset
+0.5 dB gain
+0.10 dB gain
+0.15 dB gain
+0.20 dB gain
+0.25 dB gain
+0.30 dB gain
+0.35 dB gain
+0.40 dB gain
+0.45 dB gain
+0.5 dB gain
<OFFSET TC> Time constant of offset correction in number of clock cycles (seconds, for sampling frequency =
125MSPS)
2²⁷ (1.1 s)
2²⁶ (0.55 s)
2²⁵ (0.27 s)
2²⁴ (0.13 s)
2²⁸ (2.15 s)
2²⁹ (4.3 s)
2²⁷ (1.1 s)
2²⁷ (1.1 s)
<LOW LATENCY>
Default latency, 13 clock cycles
Low latency enabled, 9 clock cycles – Digital Processing Block is bypassed.
Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS62P15
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