ADS62P15_1 Datasheet, PDF (33/63 Pages) Texas Instruments – Dual Channel 11-Bits,125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs

ADS62P15
www.ti.com .................................................................................................................................................... SLAS572B – OCTOBER 2007 – REVISED APRIL 2009
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = 3.3V, DRVDD = 3.3V, sampling frequency = 125 MSPS, sine wave clock, 50% clock duty cycle,
–1dBFS differential analog input, internal reference mode, 0 dB gain, applies to CMOS and LVDS interfaces (unless
otherwise noted).
PERFORMANCE vs AVDD SUPPLY
88
69.0
87
SFDR
68.5
86
68.0
85
67.5
SNR
84
67.0
83 _{fIN = 70.1 MHz}
DRV_DD = 3.31 V
82
3.0
3.1
3.2
3.3
3.4
3.5
AV_DD − Supply Voltage − V
Figure 20.
66.5
66.0
3.6
G011
PERFORMANCE vs TEMPERATURE
88
69.0
f_IN = 70.1 MHz
87
68.5
SFDR
86
68.0
85
67.5
SNR
84
67.0
83
66.5
82
−40 −20
0
20
40
60
T − Temperature − °C
Figure 22.
66.0
80
G013
PERFORMANCE vs INPUT CLOCK AMPLITUDE
94
73
92 ^{fIN = 20.1 MHz}
72
90
SFDR
71
88
70
86
69
84
SNR
68
82
67
80
66
78
0.0
0.5
1.0
1.5
2.0
Input Clock Amplitude − V_PP
Figure 24.
65
2.5
G015
PERFORMANCE vs DRVDD SUPPLY
88
69.0
f_IN = 70.1 MHz
87 ^{AVDD = 3.31 V}
68.5
SFDR
86
68.0
85
67.5
SNR
84
67.0
83
66.5
82
66.0
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
DRV_DD − Supply Voltage − V
G012
Figure 21.
PERFORMANCE vs INPUT AMPLITUDE
100
100
90 f_IN = 20.1 MHz
95
80
90
70
SFDR
85
60
80
50
75
40
SNR
70
30
65
20
60
10
55
0
−60
−50
−40
−30
−20
−10
50
0
Input Amplitude − dBFS
G014
Figure 23.
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
92
71
f_IN = 20.1 MHz
90
70
88
SFDR
69
86
68
SNR
84
67
82
66
80
35
40
45
50
55
60
Input Clock Duty Cycle − %
Figure 25.
65
65
G016
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