TLC545C Datasheet, PDF (5/13 Pages) Texas Instruments – 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS

TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
recommended operating conditions
TLC545
MIN NOM
MAX
TLC546
MIN NOM
UNIT
MAX
Supply voltage, VCC
Positive reference voltage, Vref+ (see Note 2)
Negative reference voltage, Vref– (see Note 3)
Differential reference voltage, Vref+ – Vref– (see Note 3)
Analog input voltage (see Note 3)
High-level control input voltage, VIH
Low-level control input voltage, VIL
Setup time, address bits at data input before I/O CLOCK↑,
tsu(A)
Address hold time, th
Setup time, CS low before clocking in first address bit, tsu(CS)
(see Note 2)
4.75
0
– 0.1
0
0
2
200
0
5
5.5
VCC
0
VCC
VCC +0.1
VCC
VCC +0.2
VCC
0.8
3
4.75
0
– 0.1
0
0
2
400
0
3
5
5.5 V
VCC VCC +0.1
V
0
VCC
V
VCC VCC +0.2
V
VCC
V
V
0.8 V
ns
ns
System
clock
cycles
I/O CLOCK frequency, fclock(I/O)
SYSTEM CLOCK frequency, fclock(SYS)
Pulse duration, CS high during conversion, twH(CS)
0
fclock(I/O)
36
2.048
0
4 fclock(I/O)
36
1.1 MHz
2.1 MHz
System
clock
cycles
Pulse duration, SYSTEM CLOCK high, twH(SYS)
110
210
ns
Pulse duration, SYSTEM CLOCK low, twL(SYS)
100
190
ns
Pulse duration, I/O CLOCK high, twH(I/O)
200
404
ns
Pulse duration, I/O CLOCK low, twL(I/O)
200
Clock transition time
(see Note 4)
System
I/O
fclock(SYS) ≤ 1048 kHz
fclock(SYS) > 1048 kHz
fclock(I/O) ≤ 525 kHz
fclock(I/O) > 525 kHz
TLC545C, TLC546C
0
Operating free-air temperature, TA _{TLC545I, TLC546I}
– 40
404
30
20
100
40
70
0
85
– 40
ns
30
ns
20
100
ns
40
70
85 °C
NOTES:
2. To minimize errors caused by noise at CS, the internal circuitry waits for three system clock cycles (or less) after a chip select falling
edge or rising edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address
data until the minimum chip select setup time has elapsed.
3. Analog input voltages greater than that applied to REF+ convert as all “1”s (11111111), while input voltages less than that applied
to REF– convert as all “0”s (00000000). As the differential reference voltage decreases below 4.75 V, the total unadjusted error tends
to increase.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
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