TLC545C Datasheet, PDF (10/13 Pages) Texas Instruments – 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS

TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
The TLC545 and TLC546 are both complete data acquisition systems on single chips. Each includes such functions
as system clock, sample and hold, 8-bit A/D converter, data and control registers, and control logic. For flexibility and
access speed, there are four control inputs; CS, ADDRESS INPUT, I/O CLOCK, and SYSTEM CLOCK. These control
inputs and a TTL-compatible 3-state output facilitate serial communications with a microprocessor or microcomputer.
The TLC545 and TLC546 can complete conversions in a maximum of 9 and 17 µs respectively, while complete
input-conversion-output cycles can be repeated at a maximum of 13 and 25 µs, respectively.
The system clock and I/O clock are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Once a clock signal within the specification range is applied to the SYSTEM CLOCK input, the control hardware and
software need only be concerned with addressing the desired analog channel, reading the previous conversion result,
and starting the conversion by using the I/O CLOCK. SYSTEM CLOCK will drive the “conversion crunching” circuitry
so that the control hardware and software need not be concerned with this task.
When CS is high, DATA OUT is in a high-impedance condition, and ADDRESS INPUT and I/O CLOCK are disabled.
This feature allows each of these terminals, with the exception of CS, to share a control logic point with their
counterpart terminals on additional A/D devices when additional TLC545/TLC546 devices are used. Thus, the above
feature serves to minimize the required control logic terminals when using multiple A/D devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
and then a falling edge of the SYSTEM CLOCK after a CS transition before the transition is recognized. The
MSB of the previous conversion result automatically appears on DATA OUT.
2. A new positive-logic multiplexer address is shifted in on the first five rising edges of I/O CLOCK. The MSB of
the address is shifted in first. The negative edges of these five I/O clocks shift out the second, third, fourth,
fifth, and sixth most significant bits of the previous conversion result. The on-chip sample and hold begins
sampling the newly addressed analog input after the fifth falling edge. The sampling operation basically
involves the charging of internal capacitors to the level of the analog input voltage.
3. Two clock cycles are then applied to I/O CLOCK and the seventh and eighth conversion bits are shifted out on
the negative edges of these clock cycles.
4. The final eighth clock cycle is applied to I/O CLOCK. The falling edge of this clock cycle completes the analog
sampling process and initiates the hold function. Conversion is then performed during the next 36 system
clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low for at least 36
system clock cycles to allow for the conversion function.
CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple
conversion, special care must be exercised to prevent noise glitches on the I/O CLOCK line. If glitches occur on the
I/O CLOCK line, the I/O sequence between the microprocessor/controller and the device loses synchronization. Also,
if CS is taken high, it must remain high until the end of conversion. Otherwise, a valid falling edge of CS causes a
reset condition, which aborts the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 36 system clock cycles occur. Such action yields the conversion result of the previous conversion and
not the ongoing conversion.
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