TLC545C Datasheet, PDF (3/13 Pages) Texas Instruments – 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS

typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
INPUT
A0 – A18
1 kΩ TYP
Ci = 60 pF TYP
(equivalent input
capacitance)
INPUT
A0 – A18
5 MΩ TYP
operating sequence
I/O
CLOCK
CS
ADDRESS
INPUT
1 2 34 5
Access
Cycle B
(see Note C)
67 8
Don’t Care
tconv
Sample Cycle B
See Note A
1 2 34 5 6 7 8
Access
Cycle C
Sample
Cycle C
MSB
LSB
B4 B3 B2 B1 B0
Don’t Care
twH(CS)
MSB
LSB
C4 C3 C2 C1 C0
Don’t Care
DATA
A7
OUT
MSB
(see Note B)
A6 A5 A4 A3 A2 A1 A0
A7
LSB
Previous Conversion Data A
MSB
Hi-Z State
B7 B6 B5 B4 B3 B2 B1 B0
Hi-Z
State
MSB
B7
LSB
Conversion Data B
MSB
NOTES: A. The conversion cycle, which requires 36 system clock periods, is initiated with the eighth I/O CLOCK↓ after CS↓ for the channel
whose address exists in memory at that time.
B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits
(A6–A0) will be clocked out on the first seven I/O CLOCK falling edges.
C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three system clock cycles (or less) after a chip
select transition before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the
minimum chip-select setup time has elapsed.
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