TLC2933 Datasheet, PDF (5/21 Pages) Texas Instruments – HIGH-PERFORMANCE PHASE-LOCKED LOOP

TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VDD (each supply, see Note 3)
Input voltage, VI (inputs except VCO IN)
Output current, IO (each output)
VCO control voltage at VCO IN
Lock frequency
Bias resistor, RBIAS
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
2.85
3 3.15
V
4.75
5 5.25
0
VDD V
0
± 2 mA
1
VDD V
37
55
MHz
43
100
1.8
2.7
kΩ
2.2
3
NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) be at the same voltage and
separated from each other.
electrical characteristics over recommended operating free-air temperature range, V_DD = 3 V
(unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT
VOH
High-level output voltage
IOH = – 2 mA
2.4
V
VOL
Low-level output voltage
IOL = 2 mA
0.3 V
VIT ₊
Positive input threshold voltage at TEST, VCO INHIBIT
0.9 1.5 2.1 V
II
Input current at TEST, VCO INHIBIT
VI = VDD or ground
± 1 µA
Zi(VCO _IN) Input impedance at VCO IN
VCO IN = 1/2 VDD
10
MΩ
IDD(INH) VCO supply current (inhibit)
See Note 4
0.01
1 µA
IDD(VCO) VCO supply current
See Note 5
5.1
15 mA
NOTES: 4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.
5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, RBIAS = 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT
is high.
PFD section
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT
VOH
VOL
IOZ
High-level output voltage
Low-level output voltage
High-impedance-state output current
IOH = – 2 mA
2.7
IOL = 2 mA
PFD INHIBIT = high,
VI = VDD or ground
V
0.2 V
± 1 µA
VIH
VIL
VIT ₊
Ci
Zi
IDD(Z)
IDD(PFD)
High-level input voltage at FIN–A, FIN–B
Low-level input voltage at FIN–A, FIN–B
Positive input threshold voltage at PFD INHIBIT
Input capacitance at FIN–A, FIN–B
Input impedance at FIN–A, FIN–B
High-impedance-state PFD supply current
PFD supply current
See Note 6
See Note 7
2.1
0.9 1.5
5
10
0.01
0.7
V
0.9 V
2.1 V
pF
MΩ
1 µA
4 mA
NOTES: 6. The current into LOGIC VDD when FIN–A and FIN–B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.
7. The current into LOGIC VDD when FIN–A and FIN–B = 30 MHz (VI(PP) = 3 V, rectangular wave), PFD INHIBIT = GND, PFD OUT
open, and VCO OUT is inhibited.
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