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TLC2933 Datasheet, PDF (13/21 Pages) Texas Instruments – HIGH-PERFORMANCE PHASE-LOCKED LOOP
TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
APPLICATION INFORMATION
SLAS136A – APRIL 1996 – REVISED JUNE 1997
gain of VCO and PFD
Figure 16 is a block diagram of the PLL. The
divider N value depends on the input frequency
and the desired VCO output frequency according
to the system application requirements. The Kp
and KV values are obtained from the operating
characteristics of the device as shown in
Figure 16. Kp is defined from the phase detector
VOL and VOH specifications and the equation
shown in Figure 16(b). KV is defined from
Figures 8, 9, 10, and 11 as shown in Figure 16(c).
The parameters for the block diagram with the
units are as follows:
KV : VCO gain (rad/s/V)
Kp : PFD gain (V/rad)
Kf : LPF gain (V/V)
KN : countdown divider gain (1/N)
external counter
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
Divider
(KN = 1/N)
f REF
PFD
(Kp)
TLC2933
VCO
(KV)
LPF
(Kf)
(a)
VOH
– 2π – π 0
π 2π
fMAX
VOH
VOL fMIN
Range of
Comparison
VIN MIN
VIN MAX
Kp =
VOH – VOL
4π
(b)
KV =
2π(fMAX – fMIN)
VIN MAX – VIN MIN
(c)
Figure 16. Example of a PLL Block Diagram
RBIAS
The external bias resistor sets the VCO center frequency with 1/2 VDD applied to the VCO IN terminal. For the
most accurate results, a metal-film resistor is the better choice but a carbon-composition resistor can also be
used with excellent results. A 0.22 µF capacitor should be connected from the BIAS terminal to ground as close
to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
] ǒ Ǔ ǒ Ǔ ǒ R Ǔ configurations shown in Figure 17 is as follows:
DwH 0.8 Kp KV Kf ( )
(1)
Where
Kf (∞) = the filter transfer function value at ω = ∞
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