TLC2551 Datasheet, PDF (5/23 Pages) Texas Instruments – 5 V, LOW POWER, 12-BIT, 400 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
detailed description (continued)
TLC2552 channel MUX reset cycle
The TLC2552 uses CS/FS to reset the AIN multiplexer. A short active CS/FS cycle (4–7 SCLKs) resets the MUX
to AIN0. If the CS/FS cycle is sufficient to complete the conversion (16 SCLKs plus maximum conversion time),
the MUX toggles to the next channel (see Figure 4 for timing).
sampling
The converter sample time is 12 SCLKs beginning on the 5^th SCLK received after the converter has received
an active CS or FS signal (CS/FS for the TLC2552/5).
conversion
The TLC2551 completes conversion in the following manner. The conversion is started after the 16th SCLK
edge. The conversion takes 1.4 µs using 20 MHz SCLK plus 0.1 µs overhead. Enough time (for conversion)
should be allowed before a rising CS/FS edge so that no conversion is terminated prematurely.
TLC2552 input channel selection is toggled on each rising CS /FS edge. The MUX channel can be reset to AIN0
via CS /FS as described in the earlier section and in Figure 5. The input is sampled for 12 SCLKs, converted,
and the result is presented on SDO during the next cycle. Care should also be taken to allow enough time
between samples to avoid prematurely terminating the conversion, which occurs on a rising CS /FS transition
if the conversion is not complete.
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