TLC2551 Datasheet, PDF (19/23 Pages) Texas Instruments – 5 V, LOW POWER, 12-BIT, 400 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
APPLICATION INFORMATION
simplified analog input analysis (continued)
ǒ Ǔ + ǒ ǒ ǓǓ ^{Equating equation 1 to equation 2 and solving for cycle time tc gives:}
Vs–
VS
8192
Vs
1–EXP
–tch
Rt Ci
(3)
and time to change to 1/2 LSB (equal to minimum sampling time) is:
ń + + tch (1 2 LSB) Rt Ci In(8192) Min[t(sample)]
Where:
In(8192) = 9.011
Therefore, with the values given, the time for the analog input signal to settle is:
ń + ) W tch (1 2 LSB) (Rs 0.5 k ) Ci In(8192)
(4)
+ w ^{ƪ ƫ} + ^{ǒ Ǔ This time must be less than the converter sample time shown in the timing diagrams. This is 12× SCLKs.}
t_(sample)
12
1
f (SCLK)
Min t_(sample)
tch
1
2
LSB
(5)
ƪ _{ǒ Ǔ}ƫ + _{ǒ ń Ǔ} + ^{Therefore the maximum SCLK frequency is:}
max f _SCLK
12
12
tch 1 2 LSB ^[In⁽⁸¹⁹²⁾ Rt
Ci]
(6)
maximum conversion throughput
For a supply voltage of 5 V, if the source impedance is less than 1 kΩ, and the ADC analog input capacitance
ǒ Ǔ _{t Ci is less than 50 pF, this equates to a minimum sampling time tch}
1
2
LSB
of 0.676 µs (
1 µs). Since the
ǒ Ǔ _{sampling time requires 12 SCLKs, the fastest SCLK frequency is 12 tch}
1
2
LSB
= 12 MHz for R_s ≤ 1 kΩ.
The minimal total cycle time, t_(cycle), is given as:
+ ) ) + _{ƪ ƫ} ) t_(cycle)
t_(sample)
t_c
t_(overhead)
16
Max f (SCLK)
14
f [(SCLK)]
) + _0.5 0.1 ms 3.77 ms
This is equivalent to a maximum throughput, max[fs] of 265 KSPS.
The throughput can be even higher with a smaller source impedance. When source impedance is 100 Ω, the
minimum sampling time becomes:
ń + + m tch (1 2 LSB) Rt Ci In(8192) 0.27 s
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
19