TLC2551 Datasheet, PDF (20/23 Pages) Texas Instruments – 5 V, LOW POWER, 12-BIT, 400 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

TLC2551, TLC2552, TLC2555
5 V, LOW POWER, 12-BIT, 400 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276 –MARCH 2000
APPLICATION INFORMATION
ǒ Ǔ ^{maximum conversion throughput (continued)}
The maximum SCLK frequency possible is 12/tch
1
2
LSB
= 44 MHz. Then a 20 MHz clock (maximum SCLK
frequency allowed for the internal comparator can be used. The minimal total cycle time is then reduced to:
+ ) ) + _{ƪ ƫ} ) _{ƪ ƫń} ) + t_(cycle)
t_(sample)
tc
t_overhead
16
max f (SCLK)
16
0.1 ms 2.3 ms
max f (SCLK) 2
The maximum throughput, MAX[fs], is 1/2.3 µs = 134 KSPS for this case.
Driving Source Requirements:
Driving Source
Data Converter
RS
VS
Vi ^ri
VC
+
_
Ci
ts _AMP
VI = Input Voltage at AIN
VS= External Driving Source Voltage
RS= Source Resistance
ri = Input Resistance (Mux On Resistance)
Ci = Input Capacitance
VC = Capacitance Charging Voltage
NOTE: Noise and distortion must for the source be equivalent to the resolution of the converter.
Rs must be real at the input frequency.
Figure 23. Equivalent Input Circuit Including the Driving Source
power down calculations
Total power consumption at different conversion rate f_s, (f_s ≤ MAX [f_s]) can be calculated by:
V_DD × i(AVERAGE) = V_DD [(f_S/MAX [f_s]) × i(ON) + (1–f_s/MAX [f_s]) × i(OFF)]
If V_DD = 5 V for TLC2551, and the sampling rate f_s = 10 kHz, the maximum sampling rate f_SMAX = 200 kHz
then i(ON) = ~3.5 mA operating current
and i(OFF) = ~8 µA auto-powerdown current
so V_DD × i(AVERAGE) = 5 × (0.05 × 3500 µA + 0.95 × 8 µA)
= (5 × 182.6) µW
= 0.9 mW
20
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