TI380C60A Datasheet, PDF (5/16 Pages) Texas Instruments – CMOS TOKEN-RING INTERFACE DEVICE

TI380C60A
CMOS TOKEN-RING INTERFACE DEVICE
SPWS033 – DECEMBER 1996
receiver
Figure 2 shows the arrangement of the line-receiver / equalizer circuit. The differential-input pair, RCV+ and
RCV–, is designed to be connected to a floating winding of an isolation transformer. Each is equipped with a
bias circuit to center the operating point of the differential input at approximately V_DD / 2.
The differential-input pair consists of a pair of metal oxide semiconductor field effect transistors (MOSFETs),
each with an identical current source in its source pin that is set to supply a nominal current of 1.5 mA. At low
signal levels, the gain of this pair is inversely proportional to the impedance connected between their sources
on EQ – and EQ +. A frequency-equalization network can be connected between EQ + and EQ – to provide
equalization for media signal distortion.
The internal wrap mode is provided for self-test of the device. When selected by taking WRAP low, the normal
input path is disabled by a multiplexer and a path is enabled from the DRVR+ / DRVR– pair. Receiver gain,
thresholds, and equalization are unchanged in the internal wrap mode.
VDD
LOAD
LOAD
RCV+
38
RCV–
36
DATA
WRAP
External Equalizer
EQ – _R1
R2
EQ +
40
41
DATA
From DRVR+ / DRVR–
IEQB
C1
IEQB
VSS
Figure 2. Line Receiver / Equalizer
receiver-clock recovery
The clock and data recovery in TI380C60A is performed by an advanced, digitally controlled phase-locked loop.
In contrast to the TMS38054, the PLL of the TI380C60A is digitally controlled and the loop parameters are set
by internally programmed digital constants. This results in precise control of loop parameters and requires no
external loop-filter components.
The TI380C60A implements an intelligent algorithm to determine the optimum phase position for data-sampling
and extracted clock synthesis. The resulting action of the TI380C60A can be modeled as two cascaded PLLs
as shown in Figure 3.
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