TC217 Datasheet, PDF (5/21 Pages) Texas Instruments – 1158- × 488-pixel ccd image sensor

TC217
1158- × 488-PIXEL CCD IMAGE SENSOR
SOCS015C – OCTOBER 1989 – REVISED JUNE 1996
multiplexer and storage area
After integration, the multiplexer rearranges two horizontal lines into vertical groups of three and separates and
loads the image into the storage area. Figure 3 shows the layout of the multiplexer gate and its interface to the
two field memories. Figure 4 shows the interface region between the storage area and the three serial registers.
A drain is also provided to clear the image-sensing and image-storage areas of unwanted charge. Such charge
can accumulate in the imager during the startup of operation or under special circumstances when nonstandard
TV operation is desired. The sensor’s independently addressable memories allow several different modes of
sensor operation including (1) a normal-light mode, (2) a low-light mode, and (3) a still mode. The timing for these
three modes is given in Figures 6, 7, and 8. The parallel-transfer timing is shown in Figure 9.
serial registers and amplifiers
After transfer to the serial registers (see Figure 10, which shows the horizontal timing that gives the necessary
sequence of pulses for transfer from the storage area to the serial registers), the charge is converted to a signal
voltage at the sense node and buffered with a dual-stage source follower. The three serial registers are typically
clocked 120 degrees out of phase with each serial-gate pulse supplying a detection node reset signal for one
of the other two serial gates. The readout timing, which includes the three serial pulses and the pixel clamp
pulses used in an off-chip double-correlated sampling circuit, is shown in Figure 12. The detection nodes and
amplifiers are located some distance away from the edge of the storage area. Therefore, 12 dummy elements
are incorporated at the end of each serial register to span the distance. The location of the dummy elements,
which are considered to be part of the amplifiers, is shown in the functional block diagram. A schematic of the
detection node and amplifier is given in Figure 5.
7.8 µm(H)
Clocked Barrier
Light
φ-IAG
φ-ABG
13.6 µm(V)
Virtual Barrier
Antiblooming Gate
Antiblooming
Clocking Levels
Virtual Well
Clocked Well
Accumulated Charge
Figure 1. Charge-Accumulation Process
Clocked Phase
φ-PS
Virtual Phase
Channel Stops
Figure 2. Charge-Transfer Process
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