DP83620SQE Datasheet, PDF (5/105 Pages) Texas Instruments – DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer

DP83620
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SNLS339C – JANUARY 2011 – REVISED APRIL 2013
3 Pin Descriptions
The DP83620 pins are classified into the following interface categories (each interface is described in the
sections that follow):
• Serial Management Interface
• MAC Data Interface
• Clock Interface
• LED Interface
• JTAG Interface
• Reset and Power Down
• Strap Options
• 10/100 Mb/s PMD Interface
• Power and Ground pins
NOTE
Strapping pin option. Please see Section 3.9 for strap definitions.
All DP83620 signal pins are I/O cells regardless of the particular use. The definitions below define the
functionality of the I/O cells for each pin.
Type: I
Input
Type: O Output
Type: I/O Input/Output
Type: OD Open Drain
Type: PD Internal Pulldown
Type: PU Internal Pullup
Type: S
Strapping Pin (All strap pins have weak internal pull-ups or pull-downs. If the default strap
value is to be changed then an external 2.2 kΩ resistor should be used. Please see
Section 3.9 for details.)
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Pin Descriptions
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