DP83620SQE Datasheet, PDF (28/105 Pages) Texas Instruments – DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer

DP83620
SNLS339C – JANUARY 2011 – REVISED APRIL 2013
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4.31 AC Specifications — RMII Receive Timing (Master Mode)
Parameter
Description
T2.27.1
RX_CLK, TX_CLK, CLK_OUT
Clock Period
T2.27.2
RXD[1:0], CRS_DV, RX_DV and
RX_ER output delay from
RX_CLK, TX_CLK, CLK_OUT
rising edge⁽¹⁾
T2.27.3
CRS ON delay⁽²⁾⁽³⁾
T2.27.4
CRS OFF delay⁽⁴⁾
T2.27.5
RXD[1:0] and RX_ER latency⁽⁵⁾
Notes
50 MHz Reference Clock
100BASE-TX mode
100BASE-FX mode
100BASE-TX mode
100BASE-FX mode
100BASE-TX mode
100BASE-FX mode
Min
Typ
Max
Units
20
ns
2
14
ns
18.5
bits
9
27
bits
17
38
bits
27
(1) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle
synchronously at the end of the packet to indicate CRS de-assertion.
(2) Per the RMII Specification, output delays assume a 25 pF load.
(3) CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.
(4) CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial de-assertion of CRS_DV.
(5) Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set
to the default value (01).
PMD Input
Pair
IDLE
(J/K)
Data
RX_CLK
TX_CLK
CLK_OUT
RX_DV
CRS/CRS_DV
RXD[1:0]
RX_ER
T2.27.5
T2.27.3
T2.27.2
T2.27.2
(TR)
T2.27.4
Data
T2.27.1
T2.27.2
T2.27.2
4.32 AC Specifications — RX_CLK Timing (RMII Master Mode)
Parameter
T2.28.1
T2.28.2
T2.28.3
Description
RX_CLK High Time
RX_CLK Low Time
RX_CLK Period⁽¹⁾
Notes
Min
(1) The High Time and Low Time will add up to 20 ns.
T2.28.3
T2.28.1
T2.28.2
RX_CLK
Typ
Max
Units
12
ns
8
ns
20
ns
28
Electrical Specifications
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