DP83620SQE Datasheet, PDF (16/105 Pages) Texas Instruments – DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer

DP83620
SNLS339C – JANUARY 2011 – REVISED APRIL 2013
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4.6 AC Specifications — Reset Timing
Parameter
Description
Notes
Min
Typ
Max
Units
T2.2.1
Post RESET Stabilization time prior to MDIO is pulled high for 32-bit serial
MDC preamble for register accesses management initialization
3
µs
T2.2.2
Hardware Configuration Latch-in Time Hardware Configuration Pins are
from the Deassertion of RESET (either described in the Pin Description
soft or hard)⁽¹⁾
section
3
µs
T2.2.3
Hardware Configuration pins transition
to output drivers⁽¹⁾
50
ns
T2.2.4
X1 Clock must be stable for at min.
RESET pulse width
of 1 µs during RESET pulse low
1
µs
time.
(1) It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide fast RC time
constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
Vcc
X1 clock
Hardware
RESET_N
MDC
Latch-In of Hardware
Configuration Pins
Dual Function Pins
Become Enabled As Outputs
T2.2.4
T2.2.1
32 CLOCKS
T2.2.2
T2.2.3
input
output
16
Electrical Specifications
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