CD74HC4075NSR Datasheet, PDF (5/13 Pages) Texas Instruments – High-Speed CMOS Logic Triple 3-Input OR Gate

CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
TEST
25^oC
SYMBOL CONDITIONS V_CC (V) MIN TYP MAX
Power Dissipation Capacitance C_PD
-
(Notes 3, 4)
5
-
26
-
-40^oC TO
85^oC
-55^oC TO 125^oC
MIN MAX MIN MAX UNITS
-
-
-
-
pF
HCT TYPES
Propagation Delay, Input to
t_PLH, t_PHL C_L = 50pF
4.5
Output (Figure 2)
C_L = 15pF
5
Transition Times (Figure 2)
t_TLH, t_THL C_L = 50pF
4.5
Input Capacitance
C_IN
-
-
Power Dissipation Capacitance C_PD
-
5
(Notes 3, 4)
-
-
24
-
30
-
-
9
-
-
-
-
-
-
15
-
19
-
-
-
10
-
10
-
-
28
-
-
-
-
36
ns
-
ns
22
ns
10
pF
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per gate.
4. P_D = V_CC2 f_i (C_PD + C_L) where f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
Test Circuits and Waveforms
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
t_r = 6ns
INPUT
2.7V
1.3V
0.3V
t_f = 6ns
3V
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5