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CD74HC4075NSR Datasheet, PDF (1/13 Pages) Texas Instruments – High-Speed CMOS Logic Triple 3-Input OR Gate
Data sheet acquired from Harris Semiconductor
SCHS210F
August 1997 - Revised August 2003
CD54HC4075, CD74HC4075,
CD54HCT4075, CD74HCT4075
High-Speed CMOS Logic
Triple 3-Input OR Gate
[ /Title
(CD74H
C4075,
CD74H
CT4075)
/Subject
(High
Speed
CMOS
Logic
Triple 3-
Input
Features
Description
• Buffered Inputs
•
Typical Propagation Delay:
CL = 15pF, TA = 25oC
8ns
at
VCC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The ’HC4075 and ’HCT4075 logic gates utilize silicon-gate
CMOS technology to achieve operating speeds similar to
LSTTL gates with the low power consumption of standard
CMOS integrated circuits. All devices have the ability to drive
10 LSTTL loads. The HCT logic family is functionally pin
compatible with the standard LS logic family.
Ordering Information
PART NUMBER
CD54HC4075F3A
CD54HCT4075F3A
CD74HC4075E
CD74HC4075M
CD74HC4075MT
CD74HC4075M96
CD74HC4075NSR
CD74HC4075PW
CD74HC4075PWR
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld SOP
14 Ld TSSOP
14 Ld TSSOP
CD74HC4075PWT
-55 to 125
14 Ld TSSOP
CD74HCT4075E
-55 to 125
14 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC4075, CD54HCT4075 (CERDIP)
CD74HC4075 (PDIP, SOIC, SOP, TSSOP)
CD74HCT4075 (PDIP)
TOP VIEW
2A 1
2B 2
1A 3
1B 4
1C 5
1Y 6
GND 7
14 VCC
13 3C
12 3B
11 3A
10 3Y
9 2Y
8 2C
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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