CD74HC4075NSR Datasheet, PDF (4/13 Pages) Texas Instruments – High-Speed CMOS Logic Triple 3-Input OR Gate

CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075
DC Electrical Specifications (Continued)
PARAMETER
HCT TYPES
SYMBOL
TEST
CONDITIONS
V_I (V) I_O (mA)
V_CC
(V)
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
MIN TYP MAX MIN MAX MIN MAX UNITS
High Level Input
Voltage
V_IH
-
-
4.5 to
2
-
-
2
-
2
-
V
5.5
Low Level Input
Voltage
V_IL
-
-
4.5 to
-
-
0.8
-
0.8
-
0.8
V
5.5
High Level Output
V_OH V_IH or V_IL -0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V_OL V_IH or V_IL 0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I_I
V_CC and
0
GND
5.5
-
±0.1
-
±1
-
±1
µA
Quiescent Device
Current
I_CC
V_CC or
0
5.5
-
-
2
-
20
-
40
µA
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I_CC
(Note 2)
V_CC
-2.1
-
4.5 to
-
100 360
-
450
-
490
µA
5.5
NOTE:
2. For dual-supply systems theoretical worst case (V_I = 2.4V, V_CC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
All
1.6
NOTE: Unit Load is ∆I_CC limit specified in DC Electrical Table, e.g.
360µA max at 25^oC.
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
Transition Times (Figure 1)
Input Capacitance
TEST
25^oC
SYMBOL CONDITIONS V_CC (V) MIN TYP MAX
t_PLH, t_PHL C_L = 50pF
2
-
- 100
4.5
-
-
20
6
-
-
17
C_L = 15pF
5
-
8
-
t_TLH, t_THL C_L = 50pF
2
-
-
75
4.5
-
-
15
6
-
-
13
C_IN
-
-
-
-
10
-40^oC TO
85^oC
-55^oC TO 125^oC
MIN MAX MIN MAX UNITS
-
125
-
150 ns
-
25
-
30
ns
-
21
-
26
ns
-
-
-
-
ns
-
95
-
110 ns
-
19
-
22
ns
-
16
-
19
ns
-
10
-
10
pF
4