BQ24266_15 Datasheet, PDF (5/41 Pages) Texas Instruments – bq24266 3A, 30V Standalone Single-Input, Single-Cell Switchmode Li-Ion Battery Charger

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PIN
NAME
AGND
BAT
BGATE
PIN
NUMBER
20
8, 9
11
BOOT
CE
CHG
DRV
IN
ISET
IUSB1
IUSB2
IUSB3
PG
PGND
PMID
SW
SYS
TS
2
4
13
3
18, 19
12
17
16
14
10
21,22
1
23, 24
6, 7
5
VDPM
15
Thermal PAD
–
bq24266
SLUSBY5F – JUNE 2014 – REVISED AUGUST 2015
Pin Functions
I/O
DESCRIPTION
–
Analog Ground. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.
I/O
Battery Connection. Connect to the positive pin of the battery. Bypass BAT to GND with at least 1μF of ceramic
capacitance. See Application section for additional details.
External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET to provide a very
O
low resistance discharge path. Connect BGATE to the gate of the external MOSFET. BGATE is low during high
impedance mode or when no input is connected. If no external FET is required, leave BGATE disconnected. Do
not connect BGATE to GND.
I
High Side MOSFET Gate Driver Supply. Connect 0.033µF of ceramic capacitance (voltage rating > 10V) from
BOOT to SW to supply the gate drive for the high side MOSFET.
I
IC Charge Enable Input. Drive CE high to place the part to disable charge. Drive CE low for normal operation.
CE is pulled low internally with 100kΩ.
O
Charge Status Open Drain Output. CHG is pulled low when a charge cycle starts and remains low while
charging. CHG is high impedance when the charging terminates and when when no supply exists.
Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass DRV to PGND
O
with at least a 2.2µF, 10V, X5R or better capacitor. DRV may be used to drive external loads up to 10mA. DRV
is active whenever the input is connected and V_IN > V_UVLO and V_IN > (V_BAT + V_SLP).
I
DC Input Power Supply. IN is connected to the external DC supply (AC adapter or USB port). Bypass IN to
PGND with at least a 4.7μF of ceramic capacitance.
I
Charge Current Programming Input. Connect a resistor from ISET to GND to program the fast charge current.
The charge current is programmable from 500mA to 3A.
I
USB Input Current Limit Programming Inputs. IUSB1, IUSB2 and IUSB3 program the input current limit for the
I
USB input. USB2.0 and USB3.0 current limits are available for easy implementation of these standards. Table 1
shows the settings for these inputs.
I
O
Power Good Open Drain output. PG is pulled low wehn a valid supply is connected. A valud supply is between
V_BAT+V_SLP and V_OVP. The output is high impedance if the supply is not in this range.
–
Ground pin. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.
I
High Side Bypass Connection. Connect at least 1µF of ceramic capacitance from PMID to PGND as close to the
PMID and PGND pins as possible.
O
Inductor Connection. Connect to the switched side of the external inductor. The inductance must be between
1.5µH and 2.2µH.
System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the output bulk
I
capacitors. Bypass SYS locally with at least 10μF of ceramic capacitance. The SYS rail must have at least 20µF
of total capacitance for stable operation. See Application section for additional details.
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The NTC is
I
connected from TS to GND. The TS function provides 4 thresholds for JEITA compatibility. Pull TS high to V_DRV
to disable the TS function if unused. See the NTC Monitor section for more details on operation and selecting
the resistor values.
Input DPM Programming Input. Connect a resistor divider from IN to GND with VDPM connected to the center
I
tap to program the Input Voltage based Dynamic Power Management (VIN_DPM) threshold. The input current is
reduced to maintain the supply voltage at VIN_DPM. See the Input Voltage based Dynamid Power Management
section for a detailed explanation.
There is an internal electrical connection between the exposed thermal pad and the PGND pin of the device. The
–
thermal pad must be connected to the same potential as the PGND pin on the printed circuit board. Do not use
the thermal pad as the primary ground input for the device. PGND pin must be connected to ground at all times.
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