ADS62P49_1 Datasheet, PDF (5/77 Pages) Texas Instruments – Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs

ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
www.ti.com............................................................................................................................................................. SLAS635A – APRIL 2009 – REVISED JUNE 2009
RECOMMENDED OPERATING CONDITIONS
SUPPLIES
AVDD Analog supply voltage
DRVDD Digital supply voltage
ANALOG INPUTS
Differential input voltage range
Input common-mode voltage
Voltage applied on CM in external reference mode
Maximum analog input frequency with 2 V_pp input amplitude⁽¹⁾
Maximum analog input frequency with 1 V_pp input amplitude⁽¹⁾
CLOCK INPUT
Input clock sample rate
ADS62P49 / ADS62P29
Enable low speed mode⁽²⁾
Low speed mode disabled (default mode after reset)
ADS62P48 / ADS62P28
Enable low speed mode
Low speed mode disabled (default mode after reset)
With multiplexed mode enabled⁽⁴⁾
Input clock amplitude differential (V_CLKP–V_CLKM)
Sine wave, ac-coupled
LVPECL, ac-coupled
LVDS, ac-coupled
LVCMOS, single-ended, ac-coupled
Input clock duty cycle
DIGITAL OUTPUTS
C_LOAD
R_LOAD
T_A
Maximum external load capacitance from each output pin to DRGND
Differential load resistance between the LVDS output pairs (LVDS mode)
Operating free-air temperature
MIN
3.15
1.7
1
>100
1
>100
1
0.2
40%
–40
(1) See the Theory of Operation section for information.
(2) Use register bit <ENABLE LOW SPEED MODE>, refer to the Serial Register Map section for information.
(3) With LVDS interface only; maximum recommended sample rate with CMOS interface is 210 MSPS.
(4) See the Multiplexed Output Mode section for information.
TYP MAX UNIT
3.3 3.6 V
1.8 1.9 V
2
1.5 ±0.1
1.5±0.05
500
800
V_PP
V
V
MHz
MHz
100
250 ⁽³⁾
100
210
65
MSPS
MSPS
MSPS
3
V_PP
1.6
V_PP
0.7
V_PP
3.3
V
50% 60%
5
pF
100
Ω
85 °C
Copyright © 2009, Texas Instruments Incorporated
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