ADS62P49_1 Datasheet, PDF (11/77 Pages) Texas Instruments – Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs

ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
www.ti.com............................................................................................................................................................. SLAS635A – APRIL 2009 – REVISED JUNE 2009
TIMING REQUIREMENTS – LVDS AND CMOS MODES (continued)
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, 1.5 Vpp
clock amplitude, C_LOAD = 5pF , R_LOAD = 100Ω , (unless otherwise noted).
Min and max values are across the full temperature range T_MIN = –40°C to T_MAX = 85°C, AVDD = 3.3V, DRVDD = 1.7V to
1.9V
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
t_OE
Output buffer enable (OE)
to data delay
Time to valid data after output buffer becomes active
100
ns
Table 1. LVDS Timings at Lower Sampling Frequencies
Sampling Frequency, MSPS
210
185
153
125
< 100
Enable LOW SPEED mode
1 ≤ Fs ≤ 100
Enable LOW SPEED mode
Setup Time, ns
MIN
TYP
MAX
0.75
1.1
0.9
1.25
1.15
1.55
1.6
2
2
Hold Time, ns
MIN
TYP
MAX
0.75
1.15
0.85
1.25
1.1
1.5
1.45
1.85
2
t_PDI, ns
MIN
TYP
MAX
12.6
Table 2. CMOS Timings at Lower Sampling Frequencies
Sampling Frequency, MSPS
210
190
170
150
Timings Specified With Respect to Input Clock
t_START, ns
MIN
TYP
MAX
Data Valid time, ns
MIN
TYP
MAX
2.5
1.7
2.7
1.9
2
3
0.9
2.7
3.7
6
3.6
4.6
Sampling Frequency, MSPS
170
150
125
<100
Enable LOW SPEED mode
1 ≤ Fs ≤ 100
Enable LOW SPEED mode
Timings Specified With Respect to CLKOUT
Setup Time, ns
Hold Time, ns
MIN
TYP
MAX
MIN
TYP
MAX
2.1
3.7
0.35
1.0
2.8
4.4
0.5
1.2
3.8
5.4
0.8
1.5
5
1.2
t_PDI, ns
MIN
TYP
MAX
9
Copyright © 2009, Texas Instruments Incorporated
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