TSB41AB1PAP Datasheet, PDF (49/69 Pages) Texas Instruments – IEEE 1394a-2000 ONE-PORT CABLE

TSB41AB1
IEEE 1394aĆ2000 ONEĆPORT CABLE
TRANSCEIVER/ARBITER
SLLS423I − JUNE 2000 − REVISED MARCH 2005
PRINCIPLES OF OPERATION
receive (continued)
Table 20. Receive Speed Codes
D0 −D7
DATA RATE
00XX XXXX
S100
0100 XXXX
S200
0101 0000
S400
1YYY YYYY
data-on indication
NOTE: X = Output as 0 by PHY, ignored by LLC.
Y = Output as 1 by PHY, ignored by LLC.
It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed
by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds
the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any
data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D
terminals, followed by idle on the CTL terminals, without any speed code or data being transferred. In all cases,
the TSB41AB1 sends at least one data-on indication before sending the speed code or terminating the receive
operation.
The TSB41AB1 also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization,
to the LLC. This packet is transferred to the LLC just as any other received self-ID packet. Figure 23 is the
reception timing diagram for normal packets, and Figure 24 is the reception timing diagram for null packets.
SYSCLK
00
CTL0, CTL1
01
D0–D7
XX
( 1)
( 2)
FF (Data-On)
10
( 3)
( 4)
SPD
d0
00
( 5)
dn
00
Figure 23. Normal Packet Reception Timing
The sequence of events for a normal packet reception is as follows:
1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.
Normally, the interface is idle until receive is asserted. However, the receive operation may interrupt a status
transfer operation that is in progress so that the CTL lines may change from status to receive without an
intervening idle.
2. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles
preceding the speed code.
3. Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D lines
for one cycle immediately preceding packet data. The link decodes the speed code on the first receive cycle
for which the D lines are not the data-on code. If the speed code is invalid, or indicates a speed higher than
that which the link is capable of handling, the link should ignore the subsequent data.
4. Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data
on the D lines with receive on the CTL lines for the remainder of the receive operation.
5. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.
The PHY asserts at least one cycle of idle following a receive operation.
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