TSB41AB1PAP Datasheet, PDF (18/69 Pages) Texas Instruments – IEEE 1394a-2000 ONE-PORT CABLE

TSB41AB1
IEEE 1394aĆ2000 ONEĆPORT CABLE
TRANSCEIVER/ARBITER
SLLS423I − JUNE 2000 − REVISED MARCH 2005
electrical characteristics over recommended ranges of operating conditions (unless otherwise
noted) (continued)
device
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Note 2
48
IDD
Supply current
See Note 3
See Note 4
42
mA
41
IDD(ULP) Supply current, ultralow-power mode
VDD = 3.3 V,
TA = 25°C,
Port disabled or unconnected,
PD = 0 V,
LPS = 0 V
150
µA
IDD(PD)
V(TH)
VOH
VOL
Supply current, power-down mode
Power status threshold, CPS input†
High-level output voltage, CTL0, CTL1,
D0 −D7, CNA, C/LKON, SYSCLK outputs
Low-level output voltage, CTL0, CTL1,
D0 −D7, CNA, C/LKON, SYSCLK outputs
PD = VDD,
TA= 25°C
VDD = 3.3 V,
400-kΩ resistor†
VDD = 2.7 V,
IOH = − 4 mA
VDD = 3 to 3.6 V, IOH = − 4 mA
IOL = 4 mA
150
4.7
2.2
2.8
µA
7.5
V
V
0.4
V
VOH(AJ)
VOL(AJ)
I(BH+)
I(BH−)
II
High-level Annex J output voltage, CTL0,
CTL1, D0 −D7, C/LKON, SYSCLK outputs
Low-level Annex J output voltage, CTL0,
CTL1, D0−D7, C/LKON, SYSCLK outputs
Positive peak bus holder current, D0 −D7,
CTL0 , CTL1, LREQ
Negative peak bus holder current,
D0 −D7, CTL0, CTL1, LREQ
Input current, LREQ, LPS, PD, TESTM,
SM, PC0 – PC2 inputs
Annex J: IOH = − 9 mA,
ISO = 0 V, VDD ≥ 3 V
Annex J: IOL = 9 mA,
ISO = 0 V, VDD ≥ 3 V
ISO = 3.6 V, VDD = 3.6 V,
VI = 0 V to VDD
ISO = 3.6 V, VDD = 3.6 V,
VI = 0 V to VDD
ISO = 0 V, VDD = 3.6 V
VDD−0.4
0.05
−1.0
V
0.4
V
1
mA
−0.05
mA
5
µA
IOZ
Off-state output current, CTL0, CTL1,
D0 – D7, C/LKON I/Os
VO = VDD or 0 V
±5
µA
I(IRST)
Pullup current, RESET input
VI = 1.5 V or 0 V
−90
−20
µA
I(SE−Pd) Pullup/pulldown current, SE input
VI = VDD/2 or VDD
5
50
µA
VIT+
Positive input threshold voltage, LREQ,
CTL0, CTL1, D0 – D7 inputs‡
Positive input threshold voltage, LPS
inputs
ISO = 0 V, VDD = 3 V to 3.6 V VDD/2+0.3
ISO = 0 V, VDD = 3 V to 3.6 V
Vref = 0.4 VDD
VDD/2+0.9
V
VREF+1
VIT _−
Negative input threshold voltage, LREQ,
CTL0, CTL1, D0 – D7 inputs‡
Negative input threshold voltage, LPS
inputs
ISO= 0 V, VDD = 3 V to 3.6 V VDD/2−0.9
ISO= 0 V, Vref = 0.4 VDD,
VDD = 3 V to 3.6 V
Vref+0.2
VDD/2−0.3
V
VO
TPBIAS output voltage§
At rated IO current
1.665
2.015
V
† _{Measured at cable power side of resistor}
‡ _{This parameter applicable only when ISO low}
§ _{TPBIAS is typically VDD−0.2 V when the port is not connected.}
NOTES: 2. Transmit maximum packet (one port transmitting maximum size isochronous packet – 4096 bytes, sent on every isochronous
interval, S400, data value of CCCCCCCCh), VDD = 3.3 V, TA = 25°C.
3. Receive typical packet (one port receiving DV packets on every isochronous interval, S100), VDD = 3.3 V, TA = 25°C.
4. Idle (one port transmitting cycle starts), VDD = 3.3 V, TA = 25°C.
18
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443