LM3S8930 Datasheet, PDF (488/550 Pages) Texas Instruments – Stellaris® LM3S8930 Microcontroller

Signal Tables
Table 18-2. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
PF1
61
I/O
TTL
GPIO port F bit 1.
PF2
60
I/O
TTL
GPIO port F bit 2.
PF3
59
I/O
TTL
GPIO port F bit 3.
PG0
19
I/O
TTL
GPIO port G bit 0.
PG1
18
I/O
TTL
GPIO port G bit 1.
RST
64
I
TTL
System reset input.
RXIN
37
I
Analog RXIN of the Ethernet PHY.
RXIP
40
I
Analog RXIP of the Ethernet PHY.
SSI0Clk
28
I/O
TTL
SSI module 0 clock.
SSI0Fss
29
I/O
TTL
SSI module 0 frame.
SSI0Rx
30
I
TTL
SSI module 0 receive.
SSI0Tx
31
O
TTL
SSI module 0 transmit.
SWCLK
80
I
TTL
JTAG/SWD CLK.
SWDIO
79
I/O
TTL
JTAG TMS and SWDIO.
SWO
77
O
TTL
JTAG TDO and SWO.
TCK
80
I
TTL
JTAG/SWD CLK.
TDI
78
I
TTL
JTAG TDI.
TDO
77
O
TTL
JTAG TDO and SWO.
TMS
79
I/O
TTL
JTAG TMS and SWDIO.
TRST
89
I
TTL
JTAG TRST.
TXON
46
O
Analog TXON of the Ethernet PHY.
TXOP
43
O
Analog TXOP of the Ethernet PHY.
U0Rx
26
I
TTL
UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
U0Tx
27
O
TTL
UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
VBAT
55
-
Power Power source for the Hibernation module. It is normally
connected to the positive terminal of a battery and serves as
the battery backup/Hibernation module power-source supply.
VCCPHY
36
-
Power VCC of the Ethernet PHY.
83
84
VDD
8
-
Power Positive supply for I/O and some logic.
20
32
44
56
68
81
93
VDD25
14
-
Power Positive supply for most of the logic function, including the
38
processor core and most peripherals.
62
88
488
June 22, 2010
Texas Instruments-Production Data