LM3S8930 Datasheet, PDF (456/550 Pages) Texas Instruments – Stellaris® LM3S8930 Microcontroller

Ethernet Controller
Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020
This register enables software to control the transfer of data to and from the MII Management
registers in the Ethernet PHY layer. The address, name, type, reset configuration, and functional
description of each of these registers can be found in Table 16-2 on page 442 and in “MII Management
Register Descriptions” on page 461.
In order to initiate a read transaction from the MII Management registers, the WRITE bit must be
cleared during the same cycle that the START bit is set.
In order to initiate a write transaction to the MII Management registers, the WRITE bit must be set
during the same cycle that the START bit is set.
Ethernet MAC Management Control (MACMCTL)
Base 0x4004.8000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
reserved
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
24
23
reserved
RO
RO
0
0
8
7
RO
R/W
0
0
22
21
20
RO
RO
RO
0
0
0
6
5
4
REGADR
R/W
R/W
R/W
0
0
0
19
18
17
16
RO
0
3
R/W
0
RO
RO
RO
0
0
0
2
1
0
reserved WRITE START
RO
R/W
R/W
0
0
0
Bit/Field
31:8
7:3
2
1
0
Name
reserved
REGADR
reserved
WRITE
START
Type
RO
R/W
RO
R/W
R/W
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
MII Register Address
The REGADR bit field represents the MII Management register address
for the next MII management interface transaction. Refer to
Table 16-2 on page 442 for the PHY register offsets.
Note that any address that is not valid in the register map should not be
written to and any data read should be ignored.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
MII Register Transaction Type
The WRITE bit represents the operation of the next MII management
interface transaction. If WRITE is set, the next operation is a write; if
WRITE is clear, the next transaction is a read.
0
MII Register Transaction Enable
The START bit represents the initiation of the next MII management
interface transaction. When this bit is set, the MII register located at
REGADR is read (WRITE=0) or written (WRITE=1).
456
June 22, 2010
Texas Instruments-Production Data