RM46L852 Datasheet, PDF (47/172 Pages) Texas Instruments – 16/32-Bit RISC Flash Microcontroller

RM46L852
www.ti.com
SPNS185 – SEPTEMBER 2012
3.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains
Parameter
f_GCLK
f_HCLK
f_VCLK
f_VCLK2
f_VCLK3
f_VCLKA1
f_VCLKA2
f_VCLKA3
f_VCLKA4
f_RTICLK
Table 3-1. Clock Domain Timing Specifications
Description
GCLK - CPU clock frequency
HCLK - System clock frequency
VCLK - Primary peripheral clock frequency
VCLK2 - Secondary peripheral clock
frequency
VCLK3 - Secondary peripheral clock
frequency
VCLKA1 - Primary asynchronous
peripheral clock frequency
VCLKA2 - Secondary asynchronous
peripheral clock frequency
VCLKA3 - Primary asynchronous
peripheral clock frequency
VCLKA4 - Secondary asynchronous
peripheral clock frequency
RTICLK - clock frequency
Conditions
Pipeline mode
enabled
Pipeline mode
disabled
Max
f_HCLK
220
55
110
110
110
110
110
110
110
f_VCLK
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
3.4 Wait States Required
RAM
Address Waitstates
0MHz
Data Waitstates
Flash
0MHz
Address Waitstates
0MHz
Data Waitstates
0MHz
0
0
0
0
55MHz
1
110MHz
Figure 3-1. Wait States Scheme
120MHz
2
165MHz
220MHz
220MHz
1
3
220MHz
220MHz
As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without
any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 55MHz in non-pipelined
mode.
The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait
state.
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
Device Operating Conditions
47