RM46L852 Datasheet, PDF (1/172 Pages) Texas Instruments – 16/32-Bit RISC Flash Microcontroller

RM46L852
www.ti.com
RM46L852 16/32-Bit RISC Flash Microcontroller
Check for Samples: RM46L852
SPNS185 – SEPTEMBER 2012
1 RM46L852 16/32-Bit RISC Flash Microcontroller
1.1 Features
1
• High-Performance Microcontroller for Safety
• Two High-End Timer Modules (N2HET)
Critical Applications
– N2HET1: 32 programmable channels
– Dual CPUs running in lockstep
– N2HET2: 18 programmable channels
– ECC on flash and RAM interfaces
– 160 Word Instruction RAM with parity
– Built-In Self Test for CPU and on-chip RAMs
protection each
– Error Signaling Module with Error Pin
– Each includes Hardware Angle Generator
– Voltage and Clock Monitoring
– Dedicated Transfer Units (HTU) on N2HETs
• ARM® Cortex™ – R4F 32-bit RISC CPU
• Two 10/12-bit Multi-Buffered ADC Modules
– 1.66DMIPS/MHz with 8-stage pipeline
– ADC1: 24 channels
– FPU with Single/Double Precision
– ADC2: 16 channels
– 12-Region Memory Protection Unit
– 16 shared channels
– Open Architecture with 3rd Party Support
– 64 result buffers with parity protection each
• Operating Conditions
• Multiple Communication Interfaces
– Up to 220MHz System Clock
– 10/100 Mbps Ethernet MAC (EMAC)
– Core Supply Voltage (VCC): 1.14V - 1.32V
• IEEE 802.3 compliant (3.3V-I/O only)
– I/O Supply Voltage (VCCIO): 3.0V - 3.6V
• Supports MII, RMII and MDIO
• Integrated Memory
– USB (revision 2.0 full-speed)
– 1.25MB Program Flash with ECC
• 2-port USB Specification, revision 2.0-
– 192KB RAM with ECC
– 64KB Flash for emulated EEPROM with ECC
• 16- bit External Memory Interface (EMIF)
• Common Platform Architecture
– Consistent memory map across family
– Real-Time Interrupt Timer (RTI) OS Timer
– 128-channel Vectored Interrupt Module (VIM)
– 2-channel Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller
– 16 Channels and 32 Control Packets
– Parity protection for control packet RAM
– DMA Accesses Protected by Dedicated MPU
• Frequency-Modulated Phase-Locked-Loop
(FMPLL) with Built-In Slip Detector
• Separate Non-Modulating PLL
• IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight Components
• Advanced JTAG Security Module (AJSM)
compatible host controller, based on the
OHCI Specification for USB, release 1.0
• USB device compatible with the USB
Specification, revision 2.0 and USB
Specification, revision 1.1
– Three CAN Controllers (DCAN)
• 64 mailboxes with parity protection each
• Compliant to CAN protocol version
2.0A/B
– Inter-Integrated Circuit (I²C)
– Three Multi-buffered Serial Peripheral
Interfaces (MibSPI)
• 128 Words with Parity Protection each
• 8 Transfer groups
– Up to two Standard Serial Peripheral
Interfaces (SPI)
– Two UART (SCI) interfaces, one with Local
Interconnect Network Interface (LIN 2.1)
Support
• Trace and Calibration Capabilities
• Up to 101 general purpose I/O (GIO) capable
– Parameter Overlay Module (POM)
pins
• Enhanced Timing Peripherals for Motor Control
– 16 dedicated GIO pins with interrupt
– 7 Enhanced Pulse Width Modulators (ePWM)
generation capability
– 6 Enhanced Capture (eCAP)
• Packages
– 2 Enhanced Quadrature Encoder Pulse
– 144-pin Quad Flatpack (PGE) [Green]
(eQEP)
1
– 337-Ball Grid Array (ZWT) [Green]
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue these products without notice.
Copyright © 2012, Texas Instruments Incorporated