TMS320C55_15 Datasheet, PDF (44/159 Pages) Texas Instruments – TMS320C5515 Fixed-Point Digital Signal Processor

TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
2.5.16 Supply Voltage Terminal Functions
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SIGNAL
NAME
NO.
F6
H8
CV_DD
J6
K10
L5
F7
K7
DV_DDIO
K12
N14
P3
P8
A2
A5
E6
F5
DV_DDEMIF
G5
H5
H7
J5
P2
Table 2-21. Supply Voltage Terminal Functions
TYPE ⁽¹⁾
(2)
OTHER ^{(3) (4)}
DESCRIPTION
SUPPLY VOLTAGES
PWR
1.05-V Digital Core supply voltage (60 or 75 MHz)
1.3-V Digital Core supply voltage (100 or 120 MHz)
PWR
PWR
1.8-V, 2.5-V, 2.75-V, or 3.3-V I/O power supply for non-EMIF and non-RTC I/Os
The DV_DDIO must always be powered for proper operation.
1.8-V, 2.5-V, 2.75-V, or 3.3-V EMIF I/O power supply
Note: When EMIF is not used, it is permissable to ground the DV_DDEMIF supply pins
if the following conditions are all met:
• At least one DV_DDEMIF package ball (A2, A5, E6, F5, G5, H5, H7, J5, P2) is
grounded. The others must be either floating or grounded.
• All signal pins that use DV_DDEMIF as their I/O supply voltage (i.e., all pins listed
in Table 2-8, External Memory Interface Terminal Functions), regardless of
multiplexing options, are either:
– all grounded
– all floating (not driven by any external source), or
– any combination of grounded or floating.
CV_DDRTC
C8
PWR
DV_DDRTC
F8
PWR
1.05-V thru 1.3-V RTC digital core and RTC oscillator power supply.
Note: The CV_DDRTC must always be powered by an external power source even
though RTC is not used. CV_DDRTC cannot be powered by any of the on-chip LDOs.
1.8-V, 2.5-V, 2.75-V, or 3.3-V I/O power supply for RTC_CLOCKOUT and WAKEUP
pins.
Note: The DV_DDRTC can be tied to ground (V_SS) when the RTC_CLKOUT and
WAKEUP pins are not permanently used. In this case, the WAKEUP pin must be
configured as output by software (see Table 5-24, RTCPMGT Register Bit
Descriptions).
V_{DDA_PLL}
see
1.3-V Analog PLL power supply for the system clock generator (PLLOUT ≤ 120
C10 PWR Section 4.2, ^MHz).
ROC
This signal can be powered from the ANA_LDOO pin.
USB_V_DDPLL
G8
USB_V_DD1P3
J13
see
3.3 V USB Analog PLL power supply.
S
Section 4.2,
ROC
When the USB peripheral is not used, the USB_V_DDPLL signal should be connected
to ground (V_SS).
see
1.3-V digital core power supply for USB PHY.
S
Section 4.2,
ROC
When the USB peripheral is not used, the USB_V_DD1P3 signal should be connected
to ground (V_SS).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-
supply current. Prevent this current by externally terminating it or enabling IPD/IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
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