TMS320C55_15 Datasheet, PDF (27/159 Pages) Texas Instruments – TMS320C5515 Fixed-Point Digital Signal Processor

TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
SIGNAL
NAME
LCD_D[11]/
I2S2_DX/
GP[27]/
SPI_TX
LCD_D8]/
I2S2_CLK/
GP[18]/
SPI_CLK
LCD_D[10]/
I2S2_RX/
GP[20]/
SPI_RX
LCD_D[9]/
I2S2_FS/
GP[19]/
SPI_CS0
LCD_D[15]/
UART_TXD/
GP[31]/
I2S3_DX
LCD_D[12]/
UART_RTS/
GP[28]/
I2S3_CLK
LCD_D[14]/
UART_RXD/
GP[30]/
I2S3_RX
LCD_D[13]/
UART_CTS/
GP[29]/
I2S3_FS
Table 2-10. Inter-IC Sound (I2S0 – I2S3) Terminal Functions (continued)
NO.
TYPE ⁽¹⁾
(2)
OTHER ^{(3) (4)}
DESCRIPTION
Interface 2 (I2S2)
P12 I/O/Z
IPD
DV_DDIO
BH
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
For I2S, it is I2S2 transmit data output I2S2_DX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
N10 I/O/Z
IPD
DV_DDIO
BH
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
For I2S, it is I2S2 clock input/output I2S2_CLK.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
N11 I/O/Z
IPD
DV_DDIO
BH
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
For I2S, it is I2S2 receive data input I2S2_RX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
P11 I/O/Z
IPD
DV_DDIO
BH
This pin is multiplexed between LCD Bridge, I2S2, and GPIO.
For I2S, it is I2S2 frame synchronization input/output I2S2_FS.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
Interface 3 (I2S3)
P14 I/O/Z
IPD
DV_DDIO
BH
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For I2S, it is I2S3 transmit data output I2S3_DX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
N12 I/O/Z
IPD
DV_DDIO
BH
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For I2S, it is I2S3 clock input/output I2S3_CLK.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
N13 I/O/Z
IPD
DV_DDIO
BH
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For I2S, it is I2S3 receive data input I2S3_RX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
P13 I/O/Z
IPD
DV_DDIO
BH
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For I2S, it is I2S3 frame synchronization input/output I2S3_FS.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
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