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TLC320AD50C-I Datasheet, PDF (41/53 Pages) Texas Instruments – SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION | |||
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5 Parameter Measurement Information
SCLK
2.4 V
FSD
0.8 V
SCLK Period/4
td(CH-FDL)
FS
0.8 V
NOTE A: Timing shown is for the TLC320AD50C/52C operating as the master device. The programmed data value in the FSD register is 0. D0
through D5 of control 3 register are all 0.
Figure 5â1. Master FS and FSD Timing
FS
0.8 V
td(FL-FDL)
FSD
0.8 V
NOTE A: Timing shown is for the TLC320AD50C/52C operating in the slave mode (FS and SCLK signals are generated externally). The
programmed data value in the FSD register is 0.
Figure 5â2. Slave FS to FSD Timing
SCLK
0.8 V
td(CH-FDL)
FSD
0.8 V
NOTE A: Timing shown is for the TLC320AD50C/52C operating in the slave mode (FS and SCLK signals are generated externally). There is a
data value in the FSD register greater than 18 decimal. D0 through D5 of control 3 register are greater than 17.
Figure 5â3. Master/Slave SCLK to FSD Timing
5â1
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