TLC320AD50C-I Datasheet, PDF (26/53 Pages) Texas Instruments – SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION

Data values from 1 to 17 should not be used.
CLKOUT
DX
DR
DVDD
MCLK
FSX
FSR
M/S _DIN
FS DOUT
MCLK
DIN
DOUT
MCLK
DIN
DOUT
CLKX
CLKR
TMS320C5X
TMS320C2X
TMS320C54X
Master FS
FSD
SCLK
Master
FS FSD
M/S
SCLK
Slave 1
FS FSD
M/S
SCLK
Slave 2
Figure 2–12. Master With Slaves (To DSP Interface)
P
P
P
P
S
M
S1
S2
S3
M
MCLK
DIN
DOUT
FS
M/S
SCLK
Slave 3
S
S
S1
Master FSD
Slave 1 FS
Delay 1
Delay 2
Delay 3
Delay 4
Slave 1 FSD
Slave 2 FS
Slave 2 FSD
Slave 3 FS
Slave 3 FSD
(see Note A)
128 SCLKs
NOTE A: Slave 3 FSD cannot be used.
Figure 2–13. Master-Slave Frame-Sync Timing After A Delay Has Been Programmed Into The FSD
Register (D0–D5 of Control 3 Register)
2–10