TLC320AD50C-I Datasheet, PDF (39/53 Pages) Texas Instruments – SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION

4.3.8 DAC Channel Characteristics
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Dynamic range
88
dB
Interchannel isolation
100
dB
EG Gain error, 0 dB
Idle channel narrow band noise
VO = 0 dB at 1020 Hz
0 – 4 kHz, See Note 8
± 0.3
dB
125 µV rms
VOO Output offset voltage at OUT (differential)
VO Analog output voltage, OUTP – OUTM
DIN = All 0s
RL = 600 Ω typ (see Figure 2–17) with internal
reference and full-scale digital input,
See Note 9, differential
30
mV
6 VPP
Total out of band energy (0.55 fs to 3 MHz)
–45 dB
Channel delay
18/fs
NOTES: 8. The conversion rate is 8 kHz; the-out-of-band measurement is made from 4400 Hz to 3 MHz.
9. The digital input to the DAC channel at DIN is in 2s complement format. The TLC320AD50C/52C DAC is of the voltage-type and
requires a load resistor for current to voltage conversion.
4.3.9 Power Supply, AV_DD = DV_DD = 5 V, No Load
PARAMETER
IDD (analog) Power supply current, ADC
IDD (PLL)
Power supply current, PLL
IDD (digital 1) Power supply current, digital
IDD (digital 2) Power supply current, digital, DVDD = 3 V
PD
Power dissipation
TEST CONDITIONS
Operating
Power down
Operating
Power down
Operating
Power down
Operating
Power down
Operating
H/W-power down
MIN TYP MAX UNIT
18
24
mA
1
2
4
mA
0.5
4
6 mA
10
µA
4
mA
10
µA
120 170
mW
7.5
20
4.3.10 Power-Supply Rejection, AV_DD = DV_DD = 5 V (see Note 10)
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT
AVDD Supply voltage rejection ratio, analog supply
fi = 0 to fs/2
50
DVDD Supply voltage rejection ratio, DAC channel
fi = 0 to 30 kHz
40
dB
DVDD Supply voltage rejection ratio, ADC channel
fi = 0 to 30 kHz
50
NOTE 10: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV peak-to-peak signal
applied to the appropriate supply.
4.4 Timing Characteristics (see Parameter Measurement Information)
4.4.1 Master Mode Timing Requirements
td1
tsu1
th1
td(CH–FDL)
twH
twL
Delay time, SCLK↑ to FS↓
Setup time, DIN, before SCLK low
Hold time, DIN, after SCLK low
Delay time, SCLK high to FSD low (see Figure 5–1)
Pulse duration, MCLK high
Pulse duration, MCLK low
MIN NOM MAX UNIT
0
25
20
ns
50
32
20
4–5